How to use block RAM in Xilinx?

[ravindra kalla]

CAN ANYBODY TELL ME,HOW TO USE BRAM IN XILINX.
PLEASE SEND ME GOOD REFERENCES.

PLEASE ALSO TELL HOW TO STORE ANY VALUE IN BRAM.
THANKING YOU
HAVE A NICE DAY

 

[cmos babe]

how to use block RAM

HI THIS IS EASY JUST GO TO XST USER GUIDE AND SEE THE HDL coding techniques section, you will find lot of examples including how to initialize the BRAM ...there's also an application note about BRAM in xilinx website.

 

[sanjana]

Re: how to use block RAM

Block ram can be instantiated in two ways .
one is by using the core generator provided by the xilinx.
The other way is to instantiate the component from unisim library.
I'have done the second one and it works correctly.
first u go to ur xilinx folder that comes when u instantiate xilinx software.
then goto folder VHDL (or vhdl_src)in that .
there u'll find unisim code file
u compile that and include it as a library.
now coming to code this will work .This is a 512 x 8 ram memory .for more details u see the xilinx online documentation.

[/code]
--data memory using unisim block ram
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.all;
entity dmemory is
port(read_data : out STD_LOGIC_VECTOR (7 downto 0);
address : in STD_LOGIC_VECTOR (7 downto 0);
clock,reset : in STD_ULOGIC;
write_data: in STD_LOGIC_VECTOR (7 downto 0);
memread,memwrite : in STD_LOGIC);
end dmemory;

architecture instance of dmemory is
component RAMB4_S8
generic (
INIT_00,
INIT_01,
INIT_02,
INIT_03,
INIT_04,
INIT_05,
INIT_06,
INIT_07,
INIT_08,
INIT_09,
INIT_0A,
INIT_0B,
INIT_0C,
INIT_0D,
INIT_0E,
INIT_0F : bit_vector :=X"0000000000000000000000000000000000000000000000000000000000000000"
);

port (WE,EN,RST,CLK:in std_logic;
ADDR : in STD_LOGIC_VECTOR (8 downto 0);
DI:in std_logic_vector(7 downto 0);
DOut std_logic_vector(7 downto 0));
end component;

signal logic0,logic1:std_logic;
signal temp,we:std_logic;
signal address1:std_logic_vector(8 downto 0);
signal clk:std_logic;

begin

logic1<=not reset;
temp<=memwrite xor memread;
we<=temp and (memwrite and (not memread));
address1<='0' & address;
clk<=not clock;
RAMB4_S8_INSTANCE_NAME : RAMB4_S8

generic map (
INIT_00 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123450808050406",
INIT_01 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_02 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_03 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_04 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_05 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_06 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_07 => X"0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF",
INIT_08 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210",
INIT_09 => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210",
INIT_0A => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210",
INIT_0B => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210",
INIT_0C => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210",
INIT_0D => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210",
INIT_0E => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210",
INIT_0F => X"FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210")
port map (WE =>we,EN=>logic1,RST=>reset,CLK =>clk,ADDR=>address1,DO=>read_data,DI=>write_data);
end instance;

 

[Renjith]

how to use block RAM

hi,
Xilnx ISE's Language Template neatly explains how to use the BRAM in ur design.
So check that out

 

[shekar_vlsi]

Re: how to use block RAM

checkout in the XST user guide (topic:HDL coding techniques). it is located in xilinx installation folder inside docs.

 

[mikeos84]

Re: how to use block RAM

Do any of you guys know how to initialize look up tables??? to use as memory???

 

[vahidkh6222]

how to use block RAM

if u use xilinx ISE, then simply use COREGENERATOR, it IS the most simplest and the most optimised methode i think..... it give u all the options u may think of...

 

[salma ali bakr]

Re: how to use block RAM

what is core generator please....it generates IP ....isn't that right...???
is it free??? can it be downloaded from xilinx site
thanks
Salma

 

[yego]

Re: how to use block RAM

if u use xilinx ISE, then simply use COREGENERATOR, it IS the most simplest and the most optimised methode i think..... it give u all the options u may think of...

.
And if you use the EDK you may even generate the whole system with just several mouse clicks. But you'll learn nothing .
It's just useful considering the time to market rush.
In most cases an average designer can do much better than that if given some time ( not too long, really ).
I never use the CoreGen because the code is not portable at all. Every vendor does it its own nonportable way. So if you are ever going to port your design, expect problems.

The CoreGen is included in the free ISE WebPack.

regards, yego

 

[cmos babe]

Re: how to use block RAM

what is core generator please....it generates IP ....isn't that right...???
is it free??? can it be downloaded from xilinx site
thanks
Salma

Hi ya it's included for free in the latest version of webpack ISE .