Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

help!!!!!!!!! on architecture

Status
Not open for further replies.
R

ravindra kalla

Junior Member level 2
Joined
Aug 3, 2005
Messages
24
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,519
hi,

i am making a architecture in which i am using processing element which used to calculate sum of absolute difference (SAD)of two matrics of size 4*4.In one case i have to calculate SAD of 18 matrics and in other case i have to calculate SAD of 10 matrics.So if i am using 9 processing element(each processing element is calculatind SAD of two matrics) in parallel for one case then in second case when i have to calculate SAD of 10 matrics then 4 processing element is remaining idle .IS thier any solution so that i can utilise hardware 100 percent for this process.

please give your valuable suggetion.

thanx
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top