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Recent content by ranger01

  1. R

    Voltage stress test and Burnin tests

    Hi I would like to understand more about the purpose of voltage stress and burnin tests. Based on my understanding burnin is used to catch infant mortalities by applying high toggle patterns at very high temps. Is Voltage stress done separately to stress the device in opposite polarity for...
  2. R

    False paths and MCP handling in ATPG

    Hello all, I am aware of a similar post on edaboard with this question. However I am unable to continue that thread as it is closed. Here I am asking the similar question. Will ATPG tool be able to generate patterns which simulate false paths and multi-cycle paths? I am sure false paths will...
  3. R

    Effect of SYNOPSYS_UNCONNECTED nets on coverage

    Hello DFT experts, Can I safely assume that SYNOPSYS_UNCONNECTED nets in netlist can directly affect the coverage ? Theoretically unconnected nets will block any propagation paths but I need to know if there are any good design practices available to exclude these nets from coverage analysis...
  4. R

    Causes for UO faults in ATPG

    I just defined UO faults in my question. The issue is with the tool. I had to re-target only the UO faults to detect them with higher abort.
  5. R

    Causes for UO faults in ATPG

    Hello DFT experts, UO faults are faults which are not observed at the POs. What could be the possible causes for this category of faults ? When I run analyze_faults on a UO fault in mentor, it is detected successfully, however I do not understand why it wasn't put under DI/DS bucket.
  6. R

    How to trace UO faults in Mentor's DFTVisualizer

    UO faults are faults which couldn't be observed at the POs. So you should trace forward to find the cause of UO faults.
  7. R

    controllability and observability improvement by scan design

    Here is my perspective, controllability and observability are the keys to achieve an Easy-to-test design. In complex designs controlling a deeply embedded node from PIs and observing the same node at the POs is a difficult thing. Difficulty is due to the fact that there will be huge number of...
  8. R

    difference between ATPG library and verilog library

    Hi rca, If I am not wrong, UDFM will be used in Cell Aware ATPG. My question is while defining complex std cell using UDFM aren't we increasing the number of total faults sites? Is the improvement in coverage is due to the fact that total fault sites is increased ? Also what are the other...
  9. R

    fastscan command add primary inputs

    Hi DFT experts, As I gather from Tessent manual add_primary_input command can be used to add internal nets as PIs. This would definitely help tool control the internal nets. But how can the patterns generated in this configuration be used on silicon or at chip level ? Thanks, Pavan
  10. R

    Measuring the effect of NBTI in SRAM cell

    I am facing similar issues. Please someone respond to this thread. Thanks
  11. R

    [SOLVED] Finfet based inverter netlist

    Hi VD, Could you please share the inverter netlist, you used with this experiment ? Thanks for your time. I am trying to simulate a FinFET based inverter in hspice using PTM-16nm model
  12. R

    Anyone worked with PTM-MG (e.g. 16nm hp/lstp nmos & pmos)model cards in HSPICE?

    Re: Anyone worked with PTM-MG (e.g. 16nm hp/lstp nmos & pmos)model cards in HSPICE? Hi, could you find the answer?
  13. R

    conv_std_logic_vector task in system verilog

    Could anyone point me to a task in System verilog equivalent to conv_std_logic_vector in vhdl?
  14. R

    transition delay faults and stuck-at faults

    macein, I understand the difference between Transition and stuck-at fault detections. Also as you rightly said the transition patterns will not cover all the testable fault sites. But my idea is, Generate the transition patterns to reach the target coverage for Transition faults, grep out the...
  15. R

    Need for cell aware ATPG for finfet technology.

    Thanks rca and rushabh for your informative responses. I am not exposed to distinctive requirements for testing methodology in my small career. But IMHO in a given timing path (generic case) if the pins of the gates are covered using stuck-at pattern and/or transition pattern and the paths are...
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