fastscan command add primary inputs

[ranger01]

Hi DFT experts,

As I gather from Tessent manual add_primary_input command can be used to add internal nets as PIs. This would definitely help tool control the internal nets. But how can the patterns generated in this configuration be used on silicon or at chip level ?

Thanks,
Pavan

 

[AnaKeim]

Hi Pavan,

I'm a support engineer at Mentor Graphics and will be helping you with this question.

The "add_primary_input -internal" command allows the ATPG tool to control the internal net as a primary input. By default the tool gives a P92 error if the internal pin is not constrained to a value or defined as a clock with a corresponding clock control or named capture procedure. This DRC is reported because in silicon there is no direct access to the internal pin. Is the user responsibility to make sure for every user defined internal pin the pin is either constrained to some value or defined as a clock. In timing simulation you have an option to simulate the patterns and have the testbench drive the internal nodes.

Internal pins are mainly used to define the internal clocks generated from OCC. In those cases you also have a clock control definition that describes the functionality of the internal clocks. Then ATPG generates the patterns according to the defined functionality.

Thanks,
Ana