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speed analysis
basically, there are 4 factors to decide the highest freq of a circuit:
1. in -> out delay
2. reg -> reg delay
3. in -> reg delay
4. reg -> out delay
the speed is limited by the longest delay of these four
hdl questions
stevepre is correct. Put it in another way: if you're answering your final test, write down 'b = 1' if you're facing real problem in your design, particularly for PL simulation, you will get 'x'.
blacktie cdc
In chapter 11, there is a long story on how to use BlackTie to check CDC. This tool may not be the best tool, but the principle in this chapter really helps.
cadence versus synopsys
Actually Omiga tells the reverse. Looking at EDA market today, Synopsys dominates the FE while Cadence takes over the BE. For most FE engineers, they like VCS, DC, PC, PT more, but BE engineers like encounter more.
hi guys, i'm thinking about writing down my bank acount number here as well as the password, what do you say? Or you can buy one with your own money from Chipmedia. They do this IP well.
help me for SDIO!
I don't think it is good idea to distribute SDIO spec in such an open place. For general purpose, a simplified version is enough. Pls pay attention that if someone's product data sheet reveals the detail of SDIO beyond the simplified version, he might be in trouble. I don't...
ASIC IP Core
one more thing, if you prefer the second, the IP delivery is much more complex than a pile of RTL design files. You need also provide testplan, block guide, synthesis script, etc. SoC companies are critical for the IPs they bought. Good luck !
It seems u r considering a real case, coz there should be at least one register in A/B boundary, plus, u r not running highest freq for this system. So just try PowerTheater.
the key to assertion based verification is not how to write assertions, but what assertions to add and how to add them to cover the intended feature is the most importent. Anyway, this is a good material.
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