Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
Characteriation of std cells means ,getting the timing information of every stdcell.
This is provided by load capacitence,slew etc.
In a design such timing info is given Synopsis Timing Library called .lib.
If you want to understand .Lib in detail ,please see the attachment below:
Characterization is the process in which standard cells and their corresponding informations are generated from their schematics, like .v file,.lib file, .lef file etc. so that they can be taken into full/semi custom IC design methodology from custom IC design methodology.
Sumit
For standard cell based ASIC we design a number of basic primitives (like NAND,NOR, Inverter,Mux,etc). The layout and schematic design part of this is called Library Development.. For timing and power analysis you should have all the information regarding a particular cell (e.g, for given input slew and output load how much delay it should have and power also)..This part of the Library design procedure is called characterization, in which you calculate delay and power for each library primitive for given input slew and output capacitance range....
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
