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In cadence simulation i am trying to simulate a comparator. and i am using ideal current source (or measurement case off chip or external current). Now i want to simulate this comparator with current source having some noise so that i can verify the measurement case (external current source...
Re: error while doing PEX using calibre in 65nm technology
Dear All
i have design a transconductance amplifier. done with layout of it.. cleared DRC and LVS and PEX. in PEX i m getting some warning. i m not able to understand those warning
i m attaching the file that shows warning
Dear All
i have design a transconductance amplifier. done with layout of it.. cleared DRC and LVS and PEX. in PEX i m getting some warning. i m not able to understand those warning but because of these warning i m able to generate config view.
i m attaching the error file
I am encountering the following error when I run extraction using Calibre v2011.4_14.13.
Error while compiling rules file /Application/Cadence/CadencePDK/UMC65LLRF1P8M1T0F1U/RuleDecks/Calibre/G-DF-LOGIC/G-DF-LOGIC_MIXED_MODE65N-LL_LOW_K_CALIBRE-LVS-1.7-P1.txt:
Error PEX5 on line 2302 of...
when i m running PEX using calibre i got fatal error.
Rules file must contain a CAPACITANE ORDER statement.
i m new in 65nm and i need to do layout of my circuit in 65nm. kindly help me.
hi
i have simply design a inverter in 65nm and completed layout so that i can understand all layout process in 65nm. i have cleared DRC in LVS i have given the path of rules file. and for inputs i have given file path but i not able to give correct path for layout netlist so it is giving some...
hi erikl
thanks for sending me IIP3 simulation pdf. but pdf has mentioned how to simulate in agilent. but i m simulating in cadence. and i know the normal simulation of IIP3 by using PSS or QPSS. but i want to know the test bench of TCA IIP3 simulation, because in TCA input is voltage and output...
hi
i have design a transconductor amplifier with CMFB. i have used 250K resistance for resistive divider from analog lib. now i want to replace it with UMC component. maximum resistance in UMC65nmlib is 124K so connected two resistance in series. but TCA performance degraded alot. m i doing...
hi everyone
thanks for helping
i have design TIA successfully. it is working fine 3dB BW is 15MHz. i have given isin at input. but if i m putting one more ac source voltage or current with frequency it is not working. and this ac source is not connected to TIA anywhere. why this problem is...
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