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[Moved]: LVS simulation in UMC 65nm technology using cadence

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nisha gupta

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hi
i have simply design a inverter in 65nm and completed layout so that i can understand all layout process in 65nm. i have cleared DRC in LVS i have given the path of rules file. and for inputs i have given file path but i not able to give correct path for layout netlist so it is giving some error. i m attaching the sreenshot of error message. kindly help me out .
 

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erikl

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I see there is a "blank" between inverterlayout. & calibre.gds

Guess Calibre cannot cope with blanks in file_names.
 

erikl

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Check if your schematic & layout dataBase (streamed back from GDS file) and the extracted dataBase is in your search path.
 

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