nisha gupta
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hi
i have simply design a inverter in 65nm and completed layout so that i can understand all layout process in 65nm. i have cleared DRC in LVS i have given the path of rules file. and for inputs i have given file path but i not able to give correct path for layout netlist so it is giving some error. i m attaching the sreenshot of error message. kindly help me out .
i have simply design a inverter in 65nm and completed layout so that i can understand all layout process in 65nm. i have cleared DRC in LVS i have given the path of rules file. and for inputs i have given file path but i not able to give correct path for layout netlist so it is giving some error. i m attaching the sreenshot of error message. kindly help me out .