Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I am facing a problem when i am doing Clock tree synthesis in encounter. The Encounter shows a error which is
**ERROR: (ENCCK-1044): Due to earlier errors, failed to generate consistent RouteType FE_CTS_DEFAULT.
and tool is terminated automatically.
so what changes i should do to solve...
Hi,
I wnat the spef file from Rc Extraction setup when i set in default mode of RC extract setup and run the command "extractRC" the rcout gives the spef file.butwhen i set in sign-off extraction mode and complete the flow then it show " native sign-off extraction is not available for FE_GPS...
Hi sat,
Thanks for your response,
But as you said that .tch is older file, so I should use .ict file. but in Encounter power system for rail analysis we should require power grid library. so generate the power grid library we require the .tch file and .layermap file. Is there any good cadence...
Hi,all
what is procedure to calculate the input transition time and output load capacitances for a pin of a standard cell in .lib file.so we can use this for calculating the power value from power_lut_template.because we know that if we want to match the internal power given by the tool and we...
Hi all,
New to this area, I have two questions that need your help.
1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get confused, under which input pattern does...
Thanks sobhit
But i want to known about meaning of the cut. what is the meaning of R0,R90,R180,R270 orientation. consider a corner pad then how we set the corner pad and in which orientation. what is the metal layer inside the corner pad so connectivity between rows and column is maintain.
Hello Friends,
Can anybody tell me about orientation of a standard cell or I/o pad. There is cut on one side of pad .what are the significance of that cut on a PAD.
Hello
I have faced a common problem in nano routing "NET sdclk has more than one top-level logical pin" here sdclk is a pin .There are some warning also "some pins doesn't have physical shape.so please somebody tell me what is meaning of logical pins . and how to arrange them in a design .
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
