Mahendra Kumar Jatav
Newbie level 6
Hi all,
New to this area, I have two questions that need your help.
1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get confused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?
my doubt is that how the internal power is calculated using .lib file of standard cell. because .lib file have internal power table 6*6 based on input transition time and capacitance value. so what is default value the we have choose when we didn't give any input in Encounter RTL compiler.
New to this area, I have two questions that need your help.
1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get confused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?
my doubt is that how the internal power is calculated using .lib file of standard cell. because .lib file have internal power table 6*6 based on input transition time and capacitance value. so what is default value the we have choose when we didn't give any input in Encounter RTL compiler.
