Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

power analysis of Cadence Encounter RTL Compiler comes from

Status
Not open for further replies.

Mahendra Kumar Jatav

Newbie level 6
Joined
Aug 3, 2015
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
89
Hi all,

New to this area, I have two questions that need your help.

1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get confused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?
my doubt is that how the internal power is calculated using .lib file of standard cell. because .lib file have internal power table 6*6 based on input transition time and capacitance value. so what is default value the we have choose when we didn't give any input in Encounter RTL compiler.
 

rca

Advanced Member level 4
Joined
May 20, 2010
Messages
1,485
Helped
355
Reputation
710
Reaction score
326
Trophy points
1,363
Location
Marin
Activity points
8,522
well without activity file, the tool used a percentage toggle activity on the clock defined to estimate the combinational activities and based on the liberty sum the power of each cell.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top