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Hi!
I'm trying to design PCB board for my At90s2313 RS232 and servo motor.
by the way, while I'm trying to get part from library, I can't find the 7 segment Anode type.
What should I do? should I make my own or download it form somewhere?
Thanks in advance for helping this question!
impact:583
thanks for advices
I'm using ISE8.2.03i. I use a standard parallel cable from manufacturer(Digilentinc).
I'm sure that cable is fine. because it worked great when I downloaded bit file in xc2s200.
I already did everything you said.
only one warining message pops up when I clicked...
webpack_9500_prog.exe
Hi!
I have encountered a problem while I'm downloading a program in CPLD.
I'm currently using spartan2 + DIO2 board(CPLD xc95108 C84).
this is the message I got from iMPACT.
ERROR:iMPACT:583 - '2': The idcode read from the device does not match the idcode in the bsdl...
buffer_type constraint
while I'm trying to test LED and switches on FPGA board, I have this message.
I'm currently using xilinx spartanII 208pin on board.
ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB
component:
PAD symbol "input_1" (Pad Signal = input_1)
BUF...
installation guide of xilinx edk
I found the all problems' solution for my request
1. First pop-up error " xilinx doesn't point to a ISE 8.2 " was caused by missing version information in fileset file in Xilinx folder.
2. second was "Path" problem! if anyone see this error message "Missing...
xilinx edk libportability.dll 8.2
that doesn't work!
I installed EDK after the same version of ISE.
becasue of that, I copied the missing dll file from ISE. then it worked.
however, I have confronted another problem.
sysnthesis doesn't worked in EDK.
<== see my original posting for...
Hi!
While I'm trying to generate netlist from .mhs file (EDK), I got the below error message!
Running XST synthesis ...
INFO:MDT - The following instances are synthesized with XST. The MPD option
IMP_NETLIST=TRUE indicates that a NGC file is to be produced using XST
synthesis...
libportability.dll
Hi!
After installing EDK 8.2i, this message("libportability.dll was not found" )
appears.
I had the solution tip from xilinx. however, It doesn't work!
Please give me a solution for this problem!
Thank you in advance.
I installed ise 8.2 and Edk 8.2. so there are no...
install edk.net
Hi!
I installed xilinx EDK 8.2i. installation was successful. but when I run this program,
popup window comes up and say " xilinx doesn't point to a ISE 8.2 "
what's this message meaning ? Does this mean that EDK can't find ISE 8.2 installation on my PC?
then should I...
I simulated a dural port memory with my top model.
then modelsim produced this error message!
I don't exactly understand what it means!
please make this message clear to me!
Thank you! so much!
Top level modules:
# glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps...
Hi!
I have a question about making ROM with coregen!
at Fourth step of making ROM(single port block memory) with coregen, there is a load init file option.
however, when I click on "load file", I can't find .coe file in the project fold.
Do I have to make my own .coe? or is it created...
When I make the counter with DLL, I used the below two code, but when clock goes higher, the second code didn't work. Can anyone tell me why?
thank you
first ,
process (clk, rst)
begin
if rst ='1' then
counter <= (others => '0);
elsif clk'event and clk='1' then
counter <=...
Hi!
I'm trying to instantiate the DCM into my code.
However, I don't know the function of some ports of it.
can anyone tell me what "Locked, PSDONE, PSCLK, DSSEN, PSINCDEC, PSEN,
and status[7:0]?
And what is the pro of using DCM if I use only one clk for my design?
Thanks in advance!
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