How can I solve this problem?

[lupineye]

buffer_type constraint

while I'm trying to test LED and switches on FPGA board, I have this message.
I'm currently using xilinx spartanII 208pin on board.


ERRORack:1107 - Unable to combine the following symbols into a single IOB
component:
PAD symbol "input_1" (Pad Signal = input_1)
BUF symbol "input_1_IBUF" (Output Signal = input_1_IBUF)
Each of the following constraints specifies an illegal physical site for a
component of type IOB:
Symbol "input_1" (LOC=P77)
Please correct the constraints accordingly.

the solution from xilinx website is below.
Solution 1:
The GCLK IOs can only use IBUFGs, so the tool is unable to pack a IBUF into the IOB. To work around this issue, specify that the net use an IBUFG. This can be done by instantiating it in your code or adding a BUFFER_TYPE constraint to your code with the value set to IBUFG. The syntax for these can be found in the Software Manuals

I found that my fault is that I'm trying to use GCLK as general input.

so I put the ibufg component to specify the net connected to IOPAD and BUFG.

entity simpleLEDtest is
Port ( button : in STD_LOGIC;
LED : out std_logic);
end simpleLEDtest;

architecture Behavioral of simpleLEDtest is

component ibufg
port(
i : std_logic;
o : std_logic);
end component;


signal buttontemp : std_logic;

begin


ibufg0 : ibufg port map(i=>button, o=> buttontemp);

LED <= buttontemp;

end Behavioral;

I know that I'm wrong! please give an advice for me!
I'm a self-starter of FPGA. so please leave me any advice to solve this problem

Thanks!

 

[echo47]

how to specify buffer_type in verilog

Are you using an xc2s200 chip?

I don't know VHDL well enough to successfully compile your code, so here are two Verilog examples that synthesize fine in ISE 9.1i.
Notice the BUFFER_TYPE constraint in the first example, and the IBUFG instantiation in the second example.
For VHDL constraint syntax, search your XST User Guide for "BUFFER_TYPE".

module simpleLEDtest (button, LED);
  (* LOC="P77", BUFFER_TYPE="IBUFG" *) input  button;
  (* LOC="P87" *) output LED;
  assign LED = button;
endmodule

module simpleLEDtest (button, LED);
  (* LOC="P77" *) input  button;
  (* LOC="P87" *) output LED;
  IBUFG u1 (.I(button), .O(LED));
endmodule

UPDATE: I figured out how to compile your VHDL. It needed a "library" section, and the "component" section needed "in" and "out" keywords. I added pin location constraints as attributes (you could use UCF instead). Both of these examples synthesize fine in ISE 9.1i.

library IEEE;
use IEEE.std_logic_1164.all;

entity simpleLEDtest is
  Port (
    button : in STD_LOGIC;
    LED : out std_logic );
  attribute LOC : string;
  attribute LOC of button : signal is "P77";
  attribute LOC of LED    : signal is "P87";
  attribute BUFFER_TYPE : string;
  attribute BUFFER_TYPE of button : signal is "IBUFG";
end simpleLEDtest;

architecture Behavioral of simpleLEDtest is
begin
  LED <= button;
end Behavioral;

library IEEE;
use IEEE.std_logic_1164.all;

entity simpleLEDtest is
  Port (
    button : in STD_LOGIC;
    LED : out std_logic );
  attribute LOC : string;
  attribute LOC of button : signal is "P77";
  attribute LOC of LED    : signal is "P87";
end simpleLEDtest;

architecture Behavioral of simpleLEDtest is
  component ibufg port (
    i : in std_logic;
    o : out std_logic );
  end component;
  signal buttontemp : std_logic;
begin
  ibufg0 : ibufg port map(i=>button, o=>buttontemp);
  LED <= buttontemp;
end Behavioral;

Or get the IBUFG definition from the unisim library ...

library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;

entity simpleLEDtest is
  Port (
    button : in STD_LOGIC;
    LED : out std_logic );
  attribute LOC : string;
  attribute LOC of button : signal is "P77";
  attribute LOC of LED    : signal is "P87";
end simpleLEDtest;

architecture Behavioral of simpleLEDtest is
  signal buttontemp : std_logic;
begin
  ibufg0 : ibufg port map(i=>button, o=>buttontemp);
  LED <= buttontemp;
end Behavioral;