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Hi, I am currently debuging the Bandgap and LDOs peaking at 3V power supply problem;
please refer to the attachment
the norminal VDD is 3.3V, and I look at the schematic, simulation results shows OK, no much variation with power supply change, also the phase margin of LDO is 53 degree, also...
vco leakage
In the measurement of pll chip, there is leakage current is being drawn into the vco tune port ( vco on), which result in leakage current to the loop filter and cause large reference spur and worse noise performance.
Anybody has suggestion about this?
thanks
I am talking about LC VCO, but c & L temp variation coefficient is really depend on the each process, right? also, the value of c & L will affect other performance (PN & tuning range) , right?
we just measure one bandgap voltage circuit using this type resistor series with a exteral resistor, and we calculate this onchip resistor value, comparing with the design value, it only chaged 5%. So, seems this resistor is not the main reason for the current deviation, right?
Anything else...
thanks for all the replies! the resistors used in the bias_gen has very small temperature variation but big process variation, so is it because of the process variation? BTW, why this resistor should be smaller temperature dependant?
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