do you think why the measurement bias current drop 30%

[lijulia]

comparing with the simulation result?

All the block )LNA, mixer, IFVGA ,div2)have the same problem.
Checked the dc bias for every device, looks OK, the layout for the current mirror device looks fine!

Do you think it is possible the value of the resistor which set the PTAT current in the bias_gen circuit change a lot due to the process variation? or any other reason? is there anyway to dubug it?
thx

 

[renwl]

which archtecture of bias circuit is used?
constant-gm or bandgap?

 

[lijulia]

it's ptat!
it make any difference? thx

 

[renwl]

the resistor value variation is 25% or so.
then the 30% current drop is reasonable.

 

[RickLi]

You should use resister with smaller temperature coefficient. If you can measure the value of any one of the resistor on chip (of the same type to the one you used in the bias block), you can figure out the problem.

 

[lijulia]

thanks for all the replies! the resistors used in the bias_gen has very small temperature variation but big process variation, so is it because of the process variation? BTW, why this resistor should be smaller temperature dependant?

 

[jonashat]

The only time I heard of such a deviation was due to the WPE (well proximity effect).

Basically, the transistors near the edge of the well have a different Vth compared to those far away from the edge.

 

[lijulia]

we just measure one bandgap voltage circuit using this type resistor series with a exteral resistor, and we calculate this onchip resistor value, comparing with the design value, it only chaged 5%. So, seems this resistor is not the main reason for the current deviation, right?

Anything else can I do to debug this issue?

About WPE (well proximity effect), is it only for the deep well device? thx

 

[مه&am]

Dear lijulia,

you have to use trimming resistors with switches, to minimize the effect of resistor variation

Added after 2 minutes:

i think the problem came from vbe changing