lijulia
Member level 3
comparing with the simulation result?
All the block )LNA, mixer, IFVGA ,div2)have the same problem.
Checked the dc bias for every device, looks OK, the layout for the current mirror device looks fine!
Do you think it is possible the value of the resistor which set the PTAT current in the bias_gen circuit change a lot due to the process variation? or any other reason? is there anyway to dubug it?
thx
All the block )LNA, mixer, IFVGA ,div2)have the same problem.
Checked the dc bias for every device, looks OK, the layout for the current mirror device looks fine!
Do you think it is possible the value of the resistor which set the PTAT current in the bias_gen circuit change a lot due to the process variation? or any other reason? is there anyway to dubug it?
thx