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Bandgap and LDO output has peak arund 3V, norminal VDD is 3.3V, please help,thanks

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lijulia

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Hi, I am currently debuging the Bandgap and LDOs peaking at 3V power supply problem;
please refer to the attachment
test.png

the norminal VDD is 3.3V, and I look at the schematic, simulation results shows OK, no much variation with power supply change, also the phase margin of LDO is 53 degree, also layout should be ok too.

Any body saw this peak in LDO design before?

Thanks
 

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