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Recent content by huckle189

  1. H

    sdc for jitter margin and non-jitter margins on a clock

    In sdc format, I want to specify jitter margin of 300ps and non-jitter margin of 500ps on clock - bistclk. How do I do that? Can anyone tell me the command to issue? Thanks, -huckle189
  2. H

    Opening timing report on unix without line wrap

    ----------------------------------------------- set nowrap didn't work. VI returned error: Wrap: No such option - 'set all' gives all option values. :set all gave: noautoindent nomodelines noshowmode autoprint nonumber...
  3. H

    Opening timing report on unix without line wrap

    Newbie question: I am looking at the timing report and the different columns are wrapping around in vi editor. How can I make the file more readable, that is...without the line-wraps to scroll down easily. Emacs is doing the line fold also. So is the vi editor. Thanks,
  4. H

    the priority order of synthesis constraints?

    There are many types of constraints - false, multicycle, set_input_delay, set_output_delay, etc Can anyone give a complete list of the order is which constraints have priority? Thanks,
  5. H

    what are clockgating paths

    Newbie question: What are clockgating enable paths? Are these real or false? Can you explain with example? Thanks,
  6. H

    Logic markers for stopping clock propagation

    Hi Newbie question: What are logic markers? How do they work? In my little understanding, they stop the clock propagation. How can a logic gate (like nor gate) stop the propagation of clock? Will the clock not still propagate? -thanks
  7. H

    Path Startpoint is clock pin? Why/

    I am not sure I understand. Why does clock coming into the block, come as data (because it goes to D pin and CLK pin of same flop)? Any examples of when it would be needed?
  8. H

    Path Startpoint is clock pin? Why/

    I am newbie to digital design. I am working on a ASIC design and I am analyzing some top critical paths and I am used to seeing IO pin to Reg paths or Reg to Reg or Reg to IO paths. This design has a path that says Startpoint is Clock pin and goes to a D pin of a register. If I look at the path...
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