Path Startpoint is clock pin? Why/

[huckle189]

I am newbie to digital design.
I am working on a ASIC design and I am analyzing some top critical paths and I am used to seeing IO pin to Reg paths or Reg to Reg or Reg to IO paths.
This design has a path that says Startpoint is Clock pin and goes to a D pin of a register.
If I look at the path details, I find Hold buffers inserted.
Why would a path have clock pin as startpoint? Any reason for such path to be in topmost critical paths? Is it false? seems the capture flop is clocked by same clock. I am confused. Sorry...

-huckle189

 

[rca]

you need to understand why the data path is driven by the clock.

 

[jeevan.life]

COZ the cell delay of flop also needs to be accounted for as the data has to pass from D pin..and this transition is linked with the CLK to D arc.

 

[huckle189]

I am not sure I understand. Why does clock coming into the block, come as data (because it goes to D pin and CLK pin of same flop)? Any examples of when it would be needed?

 

[lostinxlation]

There are two possibilities. Either the logic was made in a way that a clock is captured by a flop, or you interpret the timing report wrong.

Post the timing report.

 

[dftrtl]

Please go through how timing path is reported.