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Hello, my friend. Maybe this paper will help you. Please see it.
Analysis of Switched-Capacitor Common-Mode
Feedback Circuit
Ojas Choksi, Member, IEEE, and L. Richard Carley, Fellow, IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12...
Hi, i use Tetramax to generate test patterns first time. I want to know how to define a test clock when we got post-layout netlist. Who can tell me? Thanks in advacne.
Hello, my friend. I know you use synopsys dft max to insert scan in your design.
Usually we need wirte a dummy module to subsitute the clock gating cell or module. This dummy module could let the clock pin CK of DFF is active when clocks are set on. When you finish your insert scan flow, then...
Re: How to define a internal test_mode and test_se in DFT fl
I mean a internal test_mode and test_se signal, for example:
assign test_mode = bs_mode ? ( bist_en ? 1'b0 : ( scan_en ? 1'b1 : 1'b0 ) ): 1'b0 ;
in this example, bs_mode , bist_en and scan_en are all top pins. So the test_mode is a...
Hi, my friends.
I meet a problem. The front RTL coding designer design a internal test_mode and test_se signal. In DFT flow, how can i define a this kind of internal test_mode and test_se signals?
fix drc error dft
Hi, my friend.
I have solved my problem. I checked my netlist and found it has been inserted another test_mode port and data_source ports. So i reset my test_mode port setting. Now i got a good flow and got no S1 type error.
Orgial setting:
set_dft_signal -type TestMode -port...
data_source scan dft
In my dft flow, i have set this:
set_dft_configuration -fix_bidirectional enable.
I think this setting could fix bidirectional scan ports.
syndb-34
This warning is generated when the verilog write detect that there are references of SELECT_OP or GTECH components in this module. When finish compile, this warning maybe need not be cared.
scan chain dft
Hi, my friends.
When i ran the dft_drc command after scan insertion, I get the following error:
Error: Chain 12 blocked at DFF gate i_i2s0/i_i2s_rx_dpram/memory_reg_9_12_ after trace 0 cells.(S1-1)
Error: Test design rule checking reported FATAL violations. (TEST-1314)
I...
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