Question about DFT scan chain

[horzonbluz]

scan chain dft

Hi, my friends.
When i ran the dft_drc command after scan insertion, I get the following error:
Error: Chain 12 blocked at DFF gate i_i2s0/i_i2s_rx_dpram/memory_reg_9_12_ after trace 0 cells.(S1-1)
Error: Test design rule checking reported FATAL violations. (TEST-1314)
I have asked synopsys engineers about this question. They told us:
This is a problem caused by different defaults between TetraMAX and DFT Compiler.
If a bidirectional (bidi) port is used as a scan-in port, then the dft_drc command, which uses the TetraMAX DRC engine, expects a default bidi delay of 0, but DFT Compiler assumes bidi delay of 55 for the default clock period of 45-55.
Setting the default bidi delay to 0 avoids this S1 error and scan chains are
traced without any problems.

If your ASIC vendor does not have specific requirements, use the following values to achieve the best results:

create_test_clock -period 100 -waveform {45 55} clk
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40
set test_default_period 100

The key thing to remember here is that TetraMAX expects the test_default_bidir_delay to be less than the rising edge of the test clock. So, if the clock rises at 45ns, then any value less than 45ns is okay for the test_default_bidir_delay variable.
In my design, i checked the DFF(memory_reg_9_12_). This DFF is in chain 12 and chain 13, so the DFT tool treat this DFF has a bidirectional (bidi) port ? And how can i just let this DFF just in a scan chain to avoid this problem?

 

[sunilbudumuru]

scan chain

hello friend,

have u fixed that bi-di scan port as input or not. pls confirm,

-sunil budumuru

 

[horzonbluz]

data_source scan dft

In my dft flow, i have set this:
set_dft_configuration -fix_bidirectional enable.
I think this setting could fix bidirectional scan ports.

 

[sunilbudumuru]

dft number of scan chains

Hi friend,

even if u use "set_dft_configuration -fix_bidirectional enable", at a times tool might not fix the bidi's at toplevel ports. (i;ve faced the same situation for my design n i fixed them maually. )

However, u confirm once again in the "preview_dft -all" reports and the post dft netlist, whether the tool has fixed the bidi ports or not.

Else u have to fix the toplevel bidi pots manually. (particularly the scan ports. do not miss to verify the post dft netlist)

Pls let us know the status.

-Sunil Budumuru.

 

[horzonbluz]

fix drc error dft

Hi, my friend.
I have solved my problem. I checked my netlist and found it has been inserted another test_mode port and data_source ports. So i reset my test_mode port setting. Now i got a good flow and got no S1 type error.
Orgial setting:
set_dft_signal -type TestMode -port test_mode -active 1 -view existing_dft;
Now i set test_mode as below:
set_dft_signal -type TestMode -port test_mode -active 1;

 

[amar.reddy4020]

dft question on problmes

Hi friends,
I got the S1-error after when i run post-DFT drc. I wrote out my net list then i found that my

SN pin of latch which is connected to permanent-1 in functional mode is now connected to

SCLK (Scan Slave Clock). Can anyone help me in debugging this. The scan type is LSSD.

Thanks in advance