horzonbluz
Full Member level 4
scan chain dft
Hi, my friends.
When i ran the dft_drc command after scan insertion, I get the following error:
Error: Chain 12 blocked at DFF gate i_i2s0/i_i2s_rx_dpram/memory_reg_9_12_ after trace 0 cells.(S1-1)
Error: Test design rule checking reported FATAL violations. (TEST-1314)
I have asked synopsys engineers about this question. They told us:
This is a problem caused by different defaults between TetraMAX and DFT Compiler.
If a bidirectional (bidi) port is used as a scan-in port, then the dft_drc command, which uses the TetraMAX DRC engine, expects a default bidi delay of 0, but DFT Compiler assumes bidi delay of 55 for the default clock period of 45-55.
Setting the default bidi delay to 0 avoids this S1 error and scan chains are
traced without any problems.
If your ASIC vendor does not have specific requirements, use the following values to achieve the best results:
create_test_clock -period 100 -waveform {45 55} clk
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40
set test_default_period 100
The key thing to remember here is that TetraMAX expects the test_default_bidir_delay to be less than the rising edge of the test clock. So, if the clock rises at 45ns, then any value less than 45ns is okay for the test_default_bidir_delay variable.
In my design, i checked the DFF(memory_reg_9_12_). This DFF is in chain 12 and chain 13, so the DFT tool treat this DFF has a bidirectional (bidi) port ? And how can i just let this DFF just in a scan chain to avoid this problem?
Hi, my friends.
When i ran the dft_drc command after scan insertion, I get the following error:
Error: Chain 12 blocked at DFF gate i_i2s0/i_i2s_rx_dpram/memory_reg_9_12_ after trace 0 cells.(S1-1)
Error: Test design rule checking reported FATAL violations. (TEST-1314)
I have asked synopsys engineers about this question. They told us:
This is a problem caused by different defaults between TetraMAX and DFT Compiler.
If a bidirectional (bidi) port is used as a scan-in port, then the dft_drc command, which uses the TetraMAX DRC engine, expects a default bidi delay of 0, but DFT Compiler assumes bidi delay of 55 for the default clock period of 45-55.
Setting the default bidi delay to 0 avoids this S1 error and scan chains are
traced without any problems.
If your ASIC vendor does not have specific requirements, use the following values to achieve the best results:
create_test_clock -period 100 -waveform {45 55} clk
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40
set test_default_period 100
The key thing to remember here is that TetraMAX expects the test_default_bidir_delay to be less than the rising edge of the test clock. So, if the clock rises at 45ns, then any value less than 45ns is okay for the test_default_bidir_delay variable.
In my design, i checked the DFF(memory_reg_9_12_). This DFF is in chain 12 and chain 13, so the DFT tool treat this DFF has a bidirectional (bidi) port ? And how can i just let this DFF just in a scan chain to avoid this problem?