How to define a internal test_mode and test_se in DFT flow?

[horzonbluz]

Hi, my friends.
I meet a problem. The front RTL coding designer design a internal test_mode and test_se signal. In DFT flow, how can i define a this kind of internal test_mode and test_se signals?

 

[santhosh007]

Re: How to define a internal test_mode and test_se in DFT fl

you can create a top level pins called test_mode and test_se. then at the module level hookup pins to top level pins.

 

[horzonbluz]

Re: How to define a internal test_mode and test_se in DFT fl

I mean a internal test_mode and test_se signal, for example:
assign test_mode = bs_mode ? ( bist_en ? 1'b0 : ( scan_en ? 1'b1 : 1'b0 ) ): 1'b0 ;
in this example, bs_mode , bist_en and scan_en are all top pins. So the test_mode is a internal signals and internal wire.

 

[santhosh007]

my understanding is, that you are deriving the internal test_mode signal based the scan_en and the bs_mode. after synthesis you will have mux with output of inter test_mode signal. so you no need define this test_mode signal for performing the scan.may be you can called it as int_test_mode for avoiding cofusion with top level test mode signal.
correct me if i am wrong.