DC Problem : Module contains unmapped components

[omara007]

dft unmapped components

Hi Folks

I have a warning coming out of DC as follows:

Warning: Module regfile contains unmapped components.  The output netlist might not be read back into the system. (VO-12)

Why there are unmapped components ? .. and how can I map these unmapped ones ? .. what could be the reason for that warning ?

 

[horzonbluz]

syndb-34

This warning is generated when the verilog write detect that there are references of SELECT_OP or GTECH components in this module. When finish compile, this warning maybe need not be cared.

 

[omara007]

select_op

This warning is generated when the verilog write detect that there are references of SELECT_OP or GTECH components in this module. When finish compile, this warning maybe need not be cared.

I couldn't exactly get what you mean .. do you mean that although this warning may appear in the log, all module may not have any problem in being mapped ? ..

 

[aravind]

syndb34 synopsys

do u see this warning after compile command. followed by compile -incr

 

[omara007]

synopsys ummappped compoments

I only did the following 2 steps :
1. read_file -format vhdl file.vhdl
2. write -format verilog -hier -o netlist.v

and I got that warning at the end of the report.

 

[nschiku]

unmapped netlist

Hi,
Before you read in the vhdl file you need to give the technology library to which you need to map the design. After mentioning that you need to compile and then you can write out netlist.

Correct me if i am wrong.


Thanks,
Nik

 

[omara007]

dw_foundation.sldb

For sure I have specified the tech. lib. After that I did the 2 steps I mentioned .. I guess read_file is itself the compilation step.

 

[dcreddy1980]

module contains unmapped design

omara, you havent used link command, read_vhdl command doesn't have in-built compile step, so u have to specify it explicitly, if you follow the belwo steps, u shouldn't see any problem, if so let me know

1. read_file -format vhdl file.vhdl
2. link
3. compile
4. write -format verilog -hier -o netlist.v

 

[omara007]

contains unmapped components

omara, you havent used link command, read_vhdl command doesn't have in-built compile step, so u have to specify it explicitly, if you follow the belwo steps, u shouldn't see any problem, if so let me know

1. read_file -format vhdl file.vhdl
2. link
3. compile
4. write -format verilog -hier -o netlist.v

In my current synthesis script, I have effectively added link and compile commands, still I'm facing the same (module XYZ contains unmapped components)!!

Given that I have this error as well:

Error: Cannot find valid synthetic library module for operator 'MOD_UNS_OP'. (SYNDB-34)

 

[rsqf]

read_vhdl problem

omara, you havent used link command, read_vhdl command doesn't have in-built compile step, so u have to specify it explicitly, if you follow the belwo steps, u shouldn't see any problem, if so let me know

1. read_file -format vhdl file.vhdl
2. link
3. compile
4. write -format verilog -hier -o netlist.v

In my current synthesis script, I have effectively added link and compile commands, still I'm facing the same (module XYZ contains unmapped components)!!

Given that I have this error as well:

Error: Cannot find valid synthetic library module for operator 'MOD_UNS_OP'. (SYNDB-34)

In my opinion , the MOD_UNS_OP must exist in your netlist when you read your netlist generated by synthesis tools, if it is true , pls check your syhthesis rpt to find the warning and the cause.

 

[omara007]

syndb-34 synopsys

Yes, MOD_UNS_OP is there in my netlist.
Yet, I didn't get any warnings regarding this MOD_UNS_OP, other than the error mentioned before. I do have warnings, but for other things.

 

[rsqf]

select_op synopsys library

Yes, MOD_UNS_OP is there in my netlist.
Yet, I didn't get any warnings regarding this MOD_UNS_OP, other than the error mentioned before. I do have warnings, but for other things.

please check your link and other library when using DC compiler, the unmapped cell should not exist in the netlist.

 

[omara007]

select_op verilog

Yes, MOD_UNS_OP is there in my netlist.
Yet, I didn't get any warnings regarding this MOD_UNS_OP, other than the error mentioned before. I do have warnings, but for other things.

please check your link and other library when using DC compiler, the unmapped cell should not exist in the netlist.

And how can I do that ?

 

[rsqf]

dc unmapped

Yes, MOD_UNS_OP is there in my netlist.
Yet, I didn't get any warnings regarding this MOD_UNS_OP, other than the error mentioned before. I do have warnings, but for other things.

please check your link and other library when using DC compiler, the unmapped cell should not exist in the netlist.

And how can I do that ?

Tools will check and use the library which you set to mapped the instance , if there is no correct library, the tool will left the internal component in the netlist. If your lib set is correct, you can check which module called the MOD_UNS_OP, and how it works in the RTL code.

 

[sunilbudumuru]

dc compiler write netlist

hello friend,

'MOD_UNS_OP' is a design ware component.

1. Besure that the 'MOD_UNS_OP' component is in your Synopsys synthetic library (standard.sldb) file.

2. Verify whether it needs a seperate license for tht.

3. Division and modulus operators have never been standard license free DesignWare modules. the division and modulus implementations are contained in either the dw_foundation.sldb file or the dw02.sldb file (from synopsys)

So, try the following script

set synthetic_library {}
set target_library "XXX"
set link_library [list * XXX]

read_file dw_foundation.sldb (OR)
read_file dw02.sldb
..
..
read_verilog test.v
..

try this let us know the results

Sunil Budumuru
asic-dft.com