How to Control clock gating in DFT

[amar.reddy402]

clock gating dft

Hello all,
In my design i have manuallly instantiated latch based clock gating. When i do dft_drc it reports error.

Warnings: clock pin CK of DFF is not active when clocks are set on.

i did change my manually instatiated clock gating with library ICG cell,then everything goes fine.

What do i need to change to make my manually istantiated clock gating to skip warnings , and to make my design scan stitchable.

 

[jbeniston]

dft and clock gating

Do you enable the clock gater when scan mode is asserted?

i.e. or your current enable to the latch with scan enable. (Or if you have one, use a clock gating cell that has a scan enable input)

 

[ljxpjpjljx]

which tool do you use in DFT?

 

[sunilbudumuru]

Hello Friend,

You can refer to the following to get answered.

**broken link removed**

Sunil Budumuru

 

[horzonbluz]

Hello, my friend. I know you use synopsys dft max to insert scan in your design.
Usually we need wirte a dummy module to subsitute the clock gating cell or module. This dummy module could let the clock pin CK of DFF is active when clocks are set on. When you finish your insert scan flow, then use orgin clock gating cell to subsitute the dummy module. Good luck!