Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by gunnerunbeaten

  1. G

    what is different after synthesis same code in verilog and vhdl ?

    verilog code : module ones_counter #( parameter ST_DATA_W = 40 ) ( input clk, input reset, input [ST_DATA_W-1 : 0] in_data, input in_valid, output reg out_valid, output reg [6 : 0] out_data // expanded for 128-bit : [7 : 0] ); reg...
  2. G

    how to make 4 bits adder to output 5 bits ?

    std_match ,How about Resize in verilog ??
  3. G

    how to make 4 bits adder to output 5 bits ?

    Thank you so much !
  4. G

    how to make 4 bits adder to output 5 bits ?

    in verilog , this code : stage1[3:0] <= stage0[7] + stage0[6] + stage0[5] + stage0[4] + stage0[3] + stage0[2] + stage0[1] + stage0[0] ; have no problem when synthesis, but when running in FPGA , the result is fail. so I change this to VHDL : stage1(3 downto 0) <= stage0(7) + stage0(6) +...
  5. G

    how to make 4 bits adder to output 5 bits ?

    how about : 1 bit + 1 bit => 2 bits. when synthesis , i see error when " 1 bit + 1 bit " ???? - - - Updated - - - how about : 1 bit + 1 bit => 2 bits. when synthesis , i see error when " 1 bit + 1 bit " ????
  6. G

    how to make 4 bits adder to output 5 bits ?

    when i write code below : library IEEE; use IEEE.std_logic_textio.all; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ..... signal stage1 : unsigned (63 downto 0); signal stage2 : unsigned (39 downto 0); ... stage2(4 downto 0) <= stage1(7 downto 4) + stage1(3 downto 0) ; after...
  7. G

    Xilinx synthesis no error , but not map , place & route ... ?

    Hi ! i knew that error . the reason is simply , the folder implement miss file : 'makefile' . :-)
  8. G

    Xilinx synthesis no error , but not map , place & route ... ?

    i run synthesis in command line ( linux ) . the .ngc file is created , the report is : Total REAL time to Xst completion: 1864.00 secs Total CPU time to Xst completion: 1854.77 secs --> Total memory usage is 1218896 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings ...
  9. G

    how to xilinx synthesis give a Block Ram , not a load of DFF's ?

    thanks permute , i will try this .
  10. G

    how to xilinx synthesis give a Block Ram , not a load of DFF's ?

    LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY infer_bram IS GENERIC(ADDR_WIDTH : natural := 0; --number of bits wide for address D_WIDTH : natural := 0 --number of bits wide for data ); PORT( reset...
  11. G

    please help me some Quizs in syntax VHDL ?

    So, there is no error in Quiz 1 ?????
  12. G

    please help me some Quizs in syntax VHDL ?

    + case data type is unsigned : c. 2#1010# > "1010" : syntax correct : result : false ( 10 > 10 ) d. 1010 > "1010" : error + case data type signed : c. 2#1010# > "1010" : syntax correct : result true ( 10 > -6) d. 1010 > "1010" : error -- are these right ?
  13. G

    please help me some Quizs in syntax VHDL ?

    thanks ! please check for me : -------- Quiz 1 : + case data type is unsigned : a. "0110" > "1001" : syntax correct , result : false ( 6 > 9) b. "0110" > "0001001" : syntax correct , result : false ( 6 > 9) c. 2#1010# > "1010" : ? ( i dont know) d. 1010 > "1010"...
  14. G

    please help me some Quizs in syntax VHDL ?

    :-) exactly
  15. G

    please help me some Quizs in syntax VHDL ?

    -----Quiz 1 Determine whether the relational operation is syntactically correct. If yes, what is the result (i.e., true or false)? (a) "0110" > “1001” (b) "0110" > "000" (c) 2#1010# > "1010" (d) 1010 > "1010" case1 : assume that the data type is unsigned case2 : assume that the data type...
See more

Part and Inventory Search

Back
Top