what is different after synthesis same code in verilog and vhdl ?

[gunnerunbeaten]

verilog code :

module ones_counter  #(
    parameter ST_DATA_W = 40
)
(
    input clk,
    input reset,

    input [ST_DATA_W-1 : 0] in_data,
    input                   in_valid,

    output reg         out_valid,
    output reg [6 : 0] out_data // expanded for 128-bit : [7 : 0]
);

    reg valid0, valid1, valid2, valid3, valid4;
    reg [ST_DATA_W-1 : 0] stage0; 
    reg [63 : 0]          stage1;// expanded for up to 128-bit
    reg [39 : 0]          stage2; 
    reg [23 : 0]          stage3; 
    reg [13 : 0]          stage4; 

    // ------------------------------------------------
    // Ones counter 
    // ------------------------------------------------
    
    // pipeline for valid 
    always @(posedge clk or posedge reset) begin
      if (reset) begin
        valid0 <= 'b0;
        valid1 <= 'b0;
        valid2 <= 'b0;
        valid3 <= 'b0;
        valid4 <= 'b0;
        out_valid <= 'b0;
      end else begin
            valid0 <= in_valid;
            valid1 <= valid0;
            valid2 <= valid1;
            valid3 <= valid2;
            valid4 <= valid3;
            out_valid <= valid4;
      end // end if reset
    end // end always

    
	always @(posedge clk or posedge reset) begin
	  if (reset) begin
		stage0 <= 'b0;
		stage1 <= 'b0;
		stage2 <= 'b0;
		stage3 <= 'b0;
		stage4 <= 'b0;
		out_data <= 'b0;
	  end else begin
			stage0 <= in_data;
			/* simple method */
			stage1[3:0] <= {3'b000,stage0[7]} + stage0[6] + stage0[5] + stage0[4] + stage0[3] + stage0[2] + stage0[1] + stage0[0] ;
			stage1[7:4] <= {3'b000,stage0[15]} + stage0[14] + stage0[13] + stage0[12] + stage0[11] + stage0[10] + stage0[9] + stage0[8] ;
			stage1[11:8] <= {3'b000,stage0[23]} + stage0[22] + stage0[21] + stage0[20] + stage0[19] + stage0[18] + stage0[17] + stage0[16] ;
			stage1[15:12] <= {3'b000,stage0[31]} + stage0[30] + stage0[29] + stage0[28] + stage0[27] + stage0[26] + stage0[25] + stage0[24] ;
			stage1[19:16] <= {3'b000,stage0[39]} + stage0[38] + stage0[37] + stage0[36] + stage0[35] + stage0[34] + stage0[33] + stage0[32] ;
			stage1[23:20] <= {3'b000,stage0[47]} + stage0[46] + stage0[45] + stage0[44] + stage0[43] + stage0[42] + stage0[41] + stage0[40] ;
			stage1[27:24] <= {3'b000,stage0[55]} + stage0[54] + stage0[53] + stage0[52] + stage0[51] + stage0[50] + stage0[49] + stage0[48] ;
			stage1[31:28] <= {3'b000,stage0[63]} + stage0[62] + stage0[61] + stage0[60] + stage0[59] + stage0[58] + stage0[57] + stage0[56] ;
			stage1[35:32] <= {3'b000,stage0[71]} + stage0[70] + stage0[69] + stage0[68] + stage0[67] + stage0[66] + stage0[65] + stage0[64] ;
			stage1[39:36] <= {3'b000,stage0[79]} + stage0[78] + stage0[77] + stage0[76] + stage0[75] + stage0[74] + stage0[73] + stage0[72] ;

			
			stage2[4:0] <= {1'b0,stage1[7 : 4]} + stage1[3 : 0] ;
			stage2[9:5] <= {1'b0,stage1[15 : 12]} + stage1[11 : 8] ;
			stage2[14:10] <= {1'b0,stage1[23 : 20]} + stage1[19 : 16] ;
			stage2[19:15] <= {1'b0,stage1[31 : 28]} + stage1[27 : 24] ;
			stage2[24:20] <= {1'b0,stage1[39 : 36]} + stage1[35 : 32] ;

			
			stage3[5:0] <= {1'b0,stage2[9 : 5]} + stage2[4 : 0] ;
			stage3[11:6] <= {1'b0,stage2[19 : 15]} + stage2[14 : 10] ;
			stage3[16:12] <= stage2[24 : 20] ; // changed to 16

			
			stage4[6:0] <= {1'b0,stage3[11:6]} + stage3[5:0];
			stage4[11:7] <=stage3[16:12]; // stage4 for 80 bits
								
			out_data <= stage4[6:0] + stage4[11:7];
			
	  end // end if reset
	end // end always	
			
		
endmodule

vhdl code :

library IEEE;
use IEEE.std_logic_textio.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

ENTITY ones_counter IS
generic(
    ST_DATA_W : integer := 40
);
port (
    clk : in std_logic;
    reset : in std_logic;

    in_data : in std_logic_vector (ST_DATA_W-1 downto 0);
    in_valid : in std_logic;

    out_valid : out std_logic;
    out_data : out std_logic_vector (6 downto 0)
);
END ones_counter;



ARCHITECTURE behav OF ones_counter IS

----------------------------
---   Signal  declaration
----------------------------
signal valid0 : std_logic;
signal valid1 : std_logic;
signal valid2 : std_logic;
signal valid3 : std_logic;
signal valid4 : std_logic;

signal stage0 : unsigned (ST_DATA_W-1 downto 0);
signal stage1 : unsigned (63 downto 0);
signal stage2 : unsigned (39 downto 0);
signal stage3 : unsigned (23 downto 0);
signal stage4 : unsigned (13 downto 0);



BEGIN

------------------------------------------------
--Ones counter 
------------------------------------------------
    
    process (clk)
    begin 
      if reset = '1' then
        valid0 <= '0';
        valid1 <= '0';
        valid2 <= '0';
        valid3 <= '0';
        valid4 <= '0';
        out_valid <= '0';
      else 
		valid0 <= in_valid;
		valid1 <= valid0;
		valid2 <= valid1;
		valid3 <= valid2;
		valid4 <= valid3;
		out_valid <= valid4;
        
      end if;
    end process;
    
    

    process (clk)
    begin
            
	  if reset = '1' then
		stage0 <= (others => '0');
		stage1 <= (others => '0');
		stage2 <= (others => '0');
		stage3 <= (others => '0');
		stage4 <= (others => '0');
		out_data <= (others => '0');
	  else
			stage0 <= unsigned (in_data);
			
			--/* simple method */
			stage1(3 downto 0) <= resize (stage0(7 downto 7),4) + stage0(6 downto 6) + stage0(5 downto 5) + stage0(4 downto 4) + stage0(3 downto 3) + stage0(2 downto 2) + stage0(1 downto 1) + stage0(0 downto 0) ;
			stage1(7 downto 4) <= resize (stage0(15 downto 15),4) + stage0(14 downto 14) + stage0(13 downto 13) + stage0(12 downto 12) + stage0(11 downto 11) + stage0(10 downto 10) + stage0(9 downto 9) + stage0(8 downto 8) ;
			stage1(11 downto 8) <= resize (stage0(23 downto 23),4) + stage0(22 downto 22) + stage0(21 downto 21) + stage0(20 downto 20) + stage0(19 downto 19) + stage0(18 downto 18) + stage0(17 downto 17) + stage0(16 downto 16) ;
			stage1(15 downto 12) <= resize (stage0(31 downto 31),4) + stage0(30 downto 30) + stage0(29 downto 29) + stage0(28 downto 28) + stage0(27 downto 27) + stage0(26 downto 26) + stage0(25 downto 25) + stage0(24 downto 24) ;
			stage1(19 downto 16) <= resize (stage0(39 downto 39),4) + stage0(38 downto 38) + stage0(37 downto 37) + stage0(36 downto 36) + stage0(35 downto 35) + stage0(34 downto 34) + stage0(33 downto 33) + stage0(32 downto 32) ;
			stage1(23 downto 20) <= resize (stage0(47 downto 47),4) + stage0(46 downto 46) + stage0(45 downto 45) + stage0(44 downto 44) + stage0(43 downto 43) + stage0(42 downto 42) + stage0(41 downto 41) + stage0(40 downto 40) ;
			stage1(27 downto 24) <= resize (stage0(55 downto 55),4) + stage0(54 downto 54) + stage0(53 downto 53) + stage0(52 downto 52) + stage0(51 downto 51) + stage0(50 downto 50) + stage0(49 downto 49) + stage0(48 downto 48) ;
			stage1(31 downto 28) <= resize (stage0(63 downto 63),4) + stage0(62 downto 62) + stage0(61 downto 61) + stage0(60 downto 60) + stage0(59 downto 59) + stage0(58 downto 58) + stage0(57 downto 57) + stage0(56 downto 56) ;
			stage1(35 downto 32) <= resize (stage0(71 downto 71),4) + stage0(70 downto 70) + stage0(69 downto 69) + stage0(68 downto 68) + stage0(67 downto 67) + stage0(66 downto 66) + stage0(65 downto 65) + stage0(64 downto 64) ;
			stage1(39 downto 36) <= resize (stage0(79 downto 79),4) + stage0(78 downto 78) + stage0(77 downto 77) + stage0(76 downto 76) + stage0(75 downto 75) + stage0(74 downto 74) + stage0(73 downto 73) + stage0(72 downto 72) ;

			
			stage2(4 downto 0) <= resize (stage1(7 downto 4),5) + stage1(3 downto 0) ;
			stage2(9 downto 5) <= resize (stage1(15 downto 12),5) + stage1(11 downto 8) ;
			stage2(14 downto 10) <= resize (stage1(23 downto 20),5) + stage1(19 downto 16) ;
			stage2(19 downto 15) <= resize (stage1(31 downto 28),5) + stage1(27 downto 24) ;
			stage2(24 downto 20) <= resize (stage1(39 downto 36),5) + stage1(35 downto 32) ;

			
			stage3(5 downto 0) <= resize (stage2(9 downto 5),6) + stage2(4 downto 0) ;
			stage3(11 downto 6) <= resize (stage2(19 downto 15),6) + stage2(14 downto 10) ;
			stage3(16 downto 12) <= stage2(24 downto 20) ; --// changed to 16

			
			stage4(6 downto 0) <= resize (stage3(11 downto 6),7) + stage3(5 downto 0);
			stage4(11 downto 7) <= stage3(16 downto 12); --// stage4 for 80 bits
								
			out_data <= std_logic_vector (stage4(6 downto 0) + stage4(11 downto 7));
				
		end if;
	end process;	
			
		
    
end behav;

after synthesis and run in FPGA board , they have different result.
vhdl code has correct result, verilog code has fail result.
what is different in synthesis by Xilinx ise ???

 

[TrickyDicky]

Well, for a start, the VHDL doesnt use the correct template for synchronous logic, so the processes dont match the Verilog always blocks. For clocked processes you need:

process(clk, reset)  --reset must be in here
begin
  if reset = '1' then -- async reset
  elsif rising_edge(clk) then
    --code
  end if;
end process;

 

[std_match]

The VHDL version will synthesize to a completely combinatorial design. The output can be correct for static input data, but the pipeline will not work.

You should use simulation. I think you quickly will find the problem in the Verilog version if you simulate it.