how to xilinx synthesis give a Block Ram , not a load of DFF's ?

[gunnerunbeaten]

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.ALL;



ENTITY infer_bram IS
   GENERIC(ADDR_WIDTH        : natural := 0;  --number of  bits wide for address
           D_WIDTH           : natural := 0  --number of bits wide for data        
           );

   PORT(
        reset : in std_logic;
        
        wclk  : in  std_logic;
		  
        we    : in  std_logic;
        d     : in  std_logic_vector(D_WIDTH-1 downto 0);
        waddr : in  std_logic_vector(ADDR_WIDTH-1 downto 0);

        rclk  : in  std_logic;
        raddr : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
        o     : out std_logic_vector(D_WIDTH-1 downto 0)
       );
      
END infer_bram;
 
ARCHITECTURE behav OF infer_bram IS
 
type mem_array is array (0 to (2**ADDR_WIDTH)-1 ) of std_logic_vector(D_WIDTH-1
downto 0) ; 
signal ram : mem_array := (others => (others => '0')); 

attribute ram_style:string;
attribute ram_style of ram:signal is "block";

BEGIN
-- infer block RAM 


wr_p: process(wclk) 
begin 
   if rising_edge(wclk) then 
	if reset = '0' then
	ram<=(others => (others => '0'));--clear Ram
	 elsif we = '1' then 
         ram(to_integer(unsigned(waddr))) <= d;
      	end if; 
   end if; 
end process wr_p; 

rd_p: process(rclk) 
begin 
   if rising_edge(rclk) then
      if reset = '0' then
         o <= (others => '0');
	
      else 
         o <= ram(to_integer(unsigned(raddr)));  
      end if; 
   end if;
end process rd_p; 

end behav;

I use this as an entity, and add it to another entity . when i synthesis , Xinlinx creat many DFF's . how to guarantee the Xilinx synthesis gives a blk_ram and not a load of DFF's ?

 

[permute]

you have resets. The block rams in existing FPGAs don't have this feature. As a result, the code synthesizes to FF's.

The reset in wr_p requires writing to all elements of the ram at once, which is not possible.

the reset in rd_p may not work either, as it would require additional logic besides just the block ram. it may work in some FPGA families though, I'm just not 100% sure.

 

[gunnerunbeaten]

you have resets. The block rams in existing FPGAs don't have this feature. As a result, the code synthesizes to FF's.

The reset in wr_p requires writing to all elements of the ram at once, which is not possible.

the reset in rd_p may not work either, as it would require additional logic besides just the block ram. it may work in some FPGA families though, I'm just not 100% sure.

thanks permute , i will try this .