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I am using a generate statement to instantiate a module which is causing an unexplained increase in are after DC synthesis.
I am using Verilog
The first snippet of code gives me a certain area
generate
module_name instance name
endgenerate
I also get the same area if I don't use the...
I am trying to run LVS using a design I created in Encounter but am receiving a number of errors. I have used the >saveNetlist -excludeLeafCells -includePowerGround command to create a netlist which includes VDD and VSS just like the layout.
My standard cells also include VBP and VBN pins...
When routing a design with Encounter, I am getting a significant amount of MinCut violations when I verify geometry. They all occur on the same layer. How can I increase the number of cuts used? The MinCut is 3 yet the actual value is 1? Can this be fixed easily?
I got this warning when back annotating an sdf file. What exactly does it mean and will it cause any problems?
ncelab: *W,SDFNL2 (,35120|7): The sum of the two annotated limits to $setuphold, $recovery or $recrem timing checks are less than zero for instance :UUTreg[6] , setting negative...
The $sdf_annotate command is for verilog only so I have to use a sdf.cmd file to back annotate the compiled SDF. This means I have to use the compiled SDF.
I've tried it with the testbench instantiating the verilog netlist as (uut). I have also tried using the wrapper method a you suggest and...
In my VHDL testbench, I have only instantiated the netlist with the top level ports.
"uut : comp port map"
But the sdf.cmd file still seems to return an error telling me this can't be found. Is the sdf.cmd file wrong? Should I also include the top level testbench entity in the scope? I've...
I am doing something similar and using a VHDL testbench. My gate level netlist is verilog. My testbench is tb.vhd and the component is intantiated in the architecture as "uut : comp port map"
For the scope I am setting "SCOPE = :uut,". But I am still receiving the error "*W,SDFSNF: Specified...
I am trying to run noise analysis and need noise libraries which are in the .cdB format as far as I am aware. I only have .lib and .lef library files. Is there a way of converting these. I know there is a make_cdb command but this seems to be for netlists and individual cells. Is there a way of...
I am trying to create an I/O assignment file to define the locations of my I/O pads. I don't have any PADs defined yet so I understand I should do this at RTL level in a top-level file.
My question is how do I know what cells to instantiate in my VHDL file? Do I use one of the PADs from the IO...
I have a .ict file and I need to create a .CapTbl file and a .tch file. I can generate the .CapTbl file using the generateCapTbl command in encounter. Is there a similar command to generate a .tch file as well.
I also have a qrcTechFile (with no extension). Should I be using this instead?
I'm running a synthesis using RTL Compiler and I need a captbl file for physical synthesis for the interconnect RC extraction models. I can find .ict files but I don't have a .captbl file. How can I create one of these or which software do I use?
In IC Compoielr, can block abstraction models and ILMs be used to instantiate multiple instances of a design that has already been routed? Or do these only relate to interface logic.
I have a small routed design which has been synthesized from VHDL. How can I create an array of these and make...
I have Placed and Routed a small design using Synopsys IC Compiler and would like to use this exact design again as part of a larger design. Is it possible to package it up at make it as an IP block so that I can just instantiate it in a larger design?
Do I create a library with this component...
In IC Compiler, using RTL synthesis, is it possible to place and route multiple instances of the same module without flattening the entire large design and P&R the entire design individually?Something like the keep_hierarchy option in the top level VHDL module?
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