# Recent content by dw_man

1. ### Why does Design Compiler increase area when using a generate statement with condition

I am using a generate statement to instantiate a module which is causing an unexplained increase in are after DC synthesis. I am using Verilog The first snippet of code gives me a certain area generate module_name instance name endgenerate I also get the same area if I don't use the...
2. ### LVS using netlist from Encounter

I am trying to run LVS using a design I created in Encounter but am receiving a number of errors. I have used the >saveNetlist -excludeLeafCells -includePowerGround command to create a netlist which includes VDD and VSS just like the layout. My standard cells also include VBP and VBN pins...
3. ### How to solve MinCut DRC violation

When routing a design with Encounter, I am getting a significant amount of MinCut violations when I verify geometry. They all occur on the same layer. How can I increase the number of cuts used? The MinCut is 3 yet the actual value is 1? Can this be fixed easily?

6. ### VHDL testbench SDF file annotation problem

In my VHDL testbench, I have only instantiated the netlist with the top level ports. "uut : comp port map" But the sdf.cmd file still seems to return an error telling me this can't be found. Is the sdf.cmd file wrong? Should I also include the top level testbench entity in the scope? I've...
7. ### VHDL testbench SDF file annotation problem

I am doing something similar and using a VHDL testbench. My gate level netlist is verilog. My testbench is tb.vhd and the component is intantiated in the architecture as "uut : comp port map" For the scope I am setting "SCOPE = :uut,". But I am still receiving the error "*W,SDFSNF: Specified...
8. ### Noise libraries for noise analysis

I am trying to run noise analysis and need noise libraries which are in the .cdB format as far as I am aware. I only have .lib and .lef library files. Is there a way of converting these. I know there is a make_cdb command but this seems to be for netlists and individual cells. Is there a way of...
9. ### Using I/O assignment file and instantiating PADs in RTL.

I am trying to create an I/O assignment file to define the locations of my I/O pads. I don't have any PADs defined yet so I understand I should do this at RTL level in a top-level file. My question is how do I know what cells to instantiate in my VHDL file? Do I use one of the PADs from the IO...
10. ### Creating a tech file from .ict file.

I have a .ict file and I need to create a .CapTbl file and a .tch file. I can generate the .CapTbl file using the generateCapTbl command in encounter. Is there a similar command to generate a .tch file as well. I also have a qrcTechFile (with no extension). Should I be using this instead?
11. ### Where can I find or generate a .captbl file?

I'm running a synthesis using RTL Compiler and I need a captbl file for physical synthesis for the interconnect RC extraction models. I can find .ict files but I don't have a .captbl file. How can I create one of these or which software do I use?
12. ### Can block abstraction models and ILMs be used to instantiate multiple instances?

In IC Compoielr, can block abstraction models and ILMs be used to instantiate multiple instances of a design that has already been routed? Or do these only relate to interface logic. I have a small routed design which has been synthesized from VHDL. How can I create an array of these and make...
13. ### Can I create an IP block for reuse?

I have Placed and Routed a small design using Synopsys IC Compiler and would like to use this exact design again as part of a larger design. Is it possible to package it up at make it as an IP block so that I can just instantiate it in a larger design? Do I create a library with this component...
14. ### Differences in route/zroute

What is the difference between the two routing methods? Why do some designs route with the classic router but not with the zrouter?
15. ### Can I P&R the same module multiple times?

In IC Compiler, using RTL synthesis, is it possible to place and route multiple instances of the same module without flattening the entire large design and P&R the entire design individually?Something like the keep_hierarchy option in the top level VHDL module?