Using I/O assignment file and instantiating PADs in RTL.

[dw_man]

I am trying to create an I/O assignment file to define the locations of my I/O pads. I don't have any PADs defined yet so I understand I should do this at RTL level in a top-level file.

My question is how do I know what cells to instantiate in my VHDL file? Do I use one of the PADs from the IO lef file, if so which ones? I have already defined the power/ground/corner pads, I just need the regular I/O pads. In my lef file I have macros such DI_P, DI_G, DI_BTB_G.

 

[rca]

You need to go through the documentation and your specification to match the pad you need for your chips.
The pad could be instantiate every where in the chip not only at the top-level file.

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The instantiation of the cell name must match the name in LEF/LIB file, to be replace during the synthesis by the liberty model, and during the simulation you need to compile the rtl model provided with your pad.