Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Due to design size constraints, I can only have a single fixed-point arithmetic unit (add/subtract/multiply/divide). I have a number of arithmetic operations I need to do in a pipeline. Based on the biggest original parameters for the multiplier which were UQ0.9 and UQ5.2 (and since...
I have a 2D array of std_logic elements as below:
type A1 is array(1 downto 0) of std_logic;
type A2 is array(7 downto 0) of A1;
signal A3 : A2 := ((0,1),(1,0),(0,0),(1,1),(0,1),(0,1),(1,0),(1,0));
Now how do I print an element of A3 in an assertion? I tried doing something like this...
I have a 17x14 signed multiplier (I use a * b) in my design which is implemented as a slow booth multiplier by the synthesis tool. However the gate count of this block is obviously very high. What ways do I have to reduce the gate count? I cannot use a serial multiplier because I do not...
vhdl signed array
FvM, thanks again for your answer. I removed the 0 concatenation to the code and tried to pass on signed data but ran into a different issue.
When I try to define an array of signed numbers, I get an error:
type matrix_2_5 is array (1 downto 0) of signed(4 downto 0)...
vhdl signed addition
FvM, thanks for the answer. Yes. I agree with you that the result is correct in both signed/unsigned situations.
I guess my confusion arises from the fact that I am trying to pass the result on to another module as follows:
output_1 : out std_logic_vector(7 downto 0)...
I have a piece of VHDL code that does signed addition of an unsigned number and a signed number. However the result is always a sum of the two magnitudes irrespective of the sign of the second operand (I expect a difference when sign is 1)
Could you please tell me what I am...
Are there any freely available utilities/shareware to encrypt VHDL source code to make it difficult for humans to modify it but let EDA tools synthesize, simulate it?
If not, what is the best tool to do this? And how much does it cost approximately?
Thanks for your help.
I have a signal defined as an enumerated type in my design.
type state is (idle, start, run, end);
signal t_state is array (3 downto 0) of state;
How do I print the value of this signal to a file during my simulation?
When I do
write(line_out, t_state) or write(line_out, t_state(0))...
I have a transparent latch between flops in my design. The enable of the latch is the output of combinational logic that has no relation to the main clock that clocks the flops. The combinational logic is derived from input pins to the chip which are triggered off the main clock.
I would like to evaluate various DFT test platforms for my asic designs. These testers can be used to verify my ATPG patterns or JTAG patterns on board quickly right at my workbench.
Has anyone had any experience using these testers? I am looking particularly at Teseda V520 and...
asic respin mask
I am not familiar with metal mask changes and the costs/difficulty associated with them.
If I want to make a functional change to my asic by disconnecting and reconnecting a few wires, can this be done using a metal mask change? Even if the wires are on multiple metal...
My SCANEN signal has a fanout of over 11000.
I have a set_false_path -from SCANEN in my constraints.
When I run optDesign in Encounter, it is not building a buffer tree on the SCANEN net. Is the false path causing the tool to ignore the fanout violation? But if I take out the false path, then...
During synthesis, we apply a dont_touch_network and false_path on the reset ports because they will be buffered using CTS in the P&R. When should we remove these constraints - at entry into the P&R tool or after floorplanning/placement and before CTS?