# VHDL signed addition does not yield correct result

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#### design_engineer

##### Newbie level 6
vhdl resize

Hello,

I have a piece of VHDL code that does signed addition of an unsigned number and a signed number. However the result is always a sum of the two magnitudes irrespective of the sign of the second operand (I expect a difference when sign is 1)

Could you please tell me what I am doing wrong. Here is my code:

include IEEE.numeric_std.all;
op1: unsigned (7 downto 0);
op2: signed (7 downto 0);
op3: signed(6 downto 0);
result: signed (41 downto 0);
sum: signed(7 downto 0);

result <= mult3 + mult2 + T1; (result is negative number represented as 2's complement)

op2 <= resize(result, "8"); -- should yield a negative number (ignore quotes, I had to put that there to defeat the smiley showing up)
op3 <= shift_right(op2, 1); -- should yield a negative number
sum <= op1(7) & (signed(op1(6 downto 0)) + op3);

If op1 = 'h0C and op3 = 'h62, I get sum = 'h6E which is not right because op3 is negative.

#### FvM

##### Super Moderator
Staff member
vhdl resize signed numeric_std

In add and sub, there's no difference between signed and unsigned operation. I don't understand, what you expect different here.
0x0c + 0x62 = 0x6e is correct, either if interpreting 0x62 and 0x6e as positive or negative numbers.
In the first case: 12 + 98 = 110, in the second 12 + (-30) = -18

If the result would be sign extended to an 8-Bit number, there's a difference, but you concenated a zero bit to the left.

The first examples aren't understandable because of missing definitions for the first line.

#### design_engineer

##### Newbie level 6

FvM, thanks for the answer. Yes. I agree with you that the result is correct in both signed/unsigned situations.

I guess my confusion arises from the fact that I am trying to pass the result on to another module as follows:

output_1 : out std_logic_vector(7 downto 0);
output_1 <= std_logic_vector(sum);

But in the other module, the data is treated as all positive (positive 110) because I cannot pass on the sign information through ports.

How can I deal with this situation? Can I have signed ports in VHDL with numeric_std library?

Thanks.

#### FvM

##### Super Moderator
Staff member
vhdl signed

You can have signed ports. But in your example, the MSB is explicitely zeroed. You must sign extend the result to get a negative 8 Bit value.

Once again, no sign information is passed or rejected by using one or the other data type. The sign is coded in the bitstream, you have to
care that the correct bit vector is assembled when assigning data of different bit width.

Many vendor IPs are using std_logic_vector to pass all signed and unsigned data. It's only a matter of how to interprete the bit vectors.

#### design_engineer

##### Newbie level 6
vhdl signed array

FvM, thanks again for your answer. I removed the 0 concatenation to the code and tried to pass on signed data but ran into a different issue.

When I try to define an array of signed numbers, I get an error:

type matrix_2_5 is array (1 downto 0) of signed(4 downto 0);
output_1 : out matrix_2_5;

output_1(0) <= resize(sum, 5);

The simulator is not able to assign the signed sum to output_1 even though both are signed. I get an error saying "Expecting an expression of type SIGNED 87".
Does VHDL 87 not support signed arrays? How do I pass on the data in this case? Do I need to have invidual data signals instead of array?

Thanks.

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