design_engineer
Newbie level 6
Hello,
I have a transparent latch between flops in my design. The enable of the latch is the output of combinational logic that has no relation to the main clock that clocks the flops. The combinational logic is derived from input pins to the chip which are triggered off the main clock.
When I write timing constraints for the design in Synopsys DC, should I
1) define a clock on the latch enable and try to time the path from the 1st flop to the latch and the latch to the 2nd flop?
2) use case analysis to make the latch transparent and not care about timing to it
3) not do anything with the latch and just constrain the flop to flop path?
Thanks for any answers.
I have a transparent latch between flops in my design. The enable of the latch is the output of combinational logic that has no relation to the main clock that clocks the flops. The combinational logic is derived from input pins to the chip which are triggered off the main clock.
When I write timing constraints for the design in Synopsys DC, should I
1) define a clock on the latch enable and try to time the path from the 1st flop to the latch and the latch to the 2nd flop?
2) use case analysis to make the latch transparent and not care about timing to it
3) not do anything with the latch and just constrain the flop to flop path?
Thanks for any answers.