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VHDL: How to convert 2D std_logic array element into string?

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design_engineer

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Hello,

I have a 2D array of std_logic elements as below:

type A1 is array(1 downto 0) of std_logic;
type A2 is array(7 downto 0) of A1;
signal A3 : A2 := ((0,1),(1,0),(0,0),(1,1),(0,1),(0,1),(1,0),(1,0));

Now how do I print an element of A3 in an assertion? I tried doing something like this:

assert false report "Element 2 of A3 is" &to_string(A3(2))& "" severity note;

But to_string is not a function in the std libraries in VHDL. Please let me how this can be done. Thanks.
 

devas

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Re: VHDL: How to convert 2D std_logic array element into str

Hi,

Maybe the image package (image_pb.vhd), written by Ben Cohen, has a function you can use for this. His website is systemverilog.us, select VHDL Models & Papers.

Devas
 

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