design_engineer
Newbie level 6
Hello,
I have a 2D array of std_logic elements as below:
type A1 is array(1 downto 0) of std_logic;
type A2 is array(7 downto 0) of A1;
signal A3 : A2 := ((0,1),(1,0),(0,0),(1,1),(0,1),(0,1),(1,0),(1,0));
Now how do I print an element of A3 in an assertion? I tried doing something like this:
assert false report "Element 2 of A3 is" &to_string(A3(2))& "" severity note;
But to_string is not a function in the std libraries in VHDL. Please let me how this can be done. Thanks.
I have a 2D array of std_logic elements as below:
type A1 is array(1 downto 0) of std_logic;
type A2 is array(7 downto 0) of A1;
signal A3 : A2 := ((0,1),(1,0),(0,0),(1,1),(0,1),(0,1),(1,0),(1,0));
Now how do I print an element of A3 in an assertion? I tried doing something like this:
assert false report "Element 2 of A3 is" &to_string(A3(2))& "" severity note;
But to_string is not a function in the std libraries in VHDL. Please let me how this can be done. Thanks.