Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
If 1ns/bit resolution of phase comparator was achieved in classical method, it require a counter with 1GHz sampling clock.
So, with classical phase detector, such as JK flipflop, we can get a phase error pulse. Then, After proportionally expanding the width of the pulse with a integral cuicuit...
prs10m.pdf
How to implement a PD for the DPLL using the time-tagging method with 1ns resolution?
I think there must be circuit to expand the phase error pulse and then sampling it with high freq. clock.
could someone kindly give me some help on how to design this circuit? Thanks in advance!
Some MCU integrates PWM module. How to implement the DAC via it.
Could someone kindly provide the C source code
and some introduction document of this kind of DAC?
thanks in advance!
How to implement the time-tagging
circuit and firmware, which has a gain of Kdet = 1bit/ns.
This phase detector with 1ns resolution is for the DPLL, including the digital loop filter.
Could someone kindly provide some materals about the time tagging circuit?
Thanks in advance!
Re: urgent: about the time tagging circuit for phase detecto
Yes. I want to measure the phase differents between two signal( Clock) with the 1ns resolution.
Maybe the FPGA or EPLD is not enough for this measure, obviously, this require 1000MHz main clock to achieve 1ns resolution.
So I think...
How to implement the time-tagging
circuit and firmware, which has a gain of Kdet = 1bit/ns.
This phase detector is for the DPLL, using the digital loop filter.
Could someone kindly provide some materals about the time tagging circuit?
Thanks in advance!
Re: how to implement the JK flipflop->edge control phase
How to implement, in VHDL or schematics?
This is use to detect phase of two clock,edge control phase detector,
which is one part of ADPLL.
Logic table: two input, one output
K-------------- J------------ out
H or L ------rise...
pll static phase error definition
I want to use EPLD or FPGA to implement the PLL.
Phase detector is a J-K flipflop, and a very high frequency clock is used to counter the pulse from PD. Then the phase error will be quantified.
The digital filter is achieved as loop filter, and it's result...
steady state phase error
This is a special PLL. There are two reference inputs with different phase.
first, the ouput signal should synch to the one reference input with zero steady phase erro.
In some condition, the synchronized reference is lost, and PLL should switch to another reference...
steady state error delay locked loop
strabush, thank a lot.
But, how to add this adjustable DC offset to the integrator?
There are no ideal intergrators, so the steady phase error could not be zero for a long time. I am confused that how to make the output signal synch to the reference input (...
pll phase error
In classic PLL theory, the steay phase error depends on the loop gain(K),and initial frequecy error(Δf). However,could the steady phase error of the PLL be settable by ourselves?
If I want the steady phase error to be 100us after locked, that is, the time offset between the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
