Question: steady phase error of the PLL

[Danielye]

pll phase error

In classic PLL theory, the steay phase error depends on the loop gain(K),and initial frequecy error(Δf). However,could the steady phase error of the PLL be settable by ourselves?


If I want the steady phase error to be 100us after locked, that is, the time offset between the rising edge of input reference and that of feedback signal divided from VCO,
How to design the architecture of the PLL.

Thanks in advance!

 

[strabush]

phase error pll

If you have an integrator in the loop filter (and an integrator can be also a current charge pump loading a capacitor), then by definition the PLL phase error is zero.
If you add a DC offset to the integrator, this will cause for an equivalent precise phase error in the PLL loop to correct the injected offset, which is what you asked for.

 

[Danielye]

steady state error delay locked loop

strabush, thank a lot.
But, how to add this adjustable DC offset to the integrator?

There are no ideal intergrators, so the steady phase error could not be zero for a long time. I am confused that how to make the output signal synch to the reference input ( zero phase error).

If the digital filter is used for the loop filter, could the ideal intergrator be implemented?

 

[biff44]

pll initial phase synchronization of two vcos

Don't confuse the two topics. Any phase locked loop with an integrator in the loop filter is CAPABLE of zero phase error, and phase locked loop without an integrator in the loop filter is doomed to a static phase error, the magnitude of which is related to the open loop gain.

What you want is somethng different. Somewhere in your system there is a phase detector. Let us assume it is a standard "charge pump" style. In this type, + current pulses come out if the phase is leading, and - current pulses come out if the phase is laging (I might have that backwards). The idea is to pump up or down the voltage across a capacitor with the + or - current pulses. If at the charge pump, you introduce a bias current, say +100 microamps, then the phase locked loop will skew its phase so that a correcting -100 microamps of current pulses is produced. This will continue indefinitely, and your phase will sit there with an offset. Unfortunately, there will be plenty of wide current pulses coming out of the phase detector, which will turn into RF Spurious sidetones of significant magnitude at the voltage controlled oscillator. If you can live with those RF spurs, you are done. If not, you will need a more complex system...

 

[Danielye]

steady state phase error

This is a special PLL. There are two reference inputs with different phase.

first, the ouput signal should synch to the one reference input with zero steady phase erro.

In some condition, the synchronized reference is lost, and PLL should switch to another reference. The point is that the phase of output signal must keep the same to the lost reference, while frequency synchronizes to the second reference.

In order to implement this system, the phase different of the two reference will be measured. When switching the reference, the PLL can hold this phase difference. This is why I want the steady phase error can be tunable.

Could you kindly provide some suggestions of architecture of this kind of PLL.

 

[biff44]

pll phase detector offset

I do not think it can be done. If the 2nd reference (the one that is always there) is not at exactly the same frequency as the first reference (the one that goes away), you will have a changing phase error with increasing time. When the first reference dissapears, the pll can lock onto the 2nd reference, but it will quickly attain any phase difference AND frequency difference imparted by the 2nd reference. Simply adding a phase offset to an unlocked 2nd reference will not help anything, except in the very short term (hundreds of milliseconds perhaps).

Also, transitioning the PLL from the first reference to the second reference is not easily done without the potential for pulse slipping, etc.

If I were doing this, I would instead have the 1st reference drive a PLL to lock the 2nd reference to it. I would then lock the output VCO only to the 2nd reference. When the 1st reference went away I would disable the charge pump of the reference PLL and let the 2nd reference free-run until the 1st reference returned. You might need a very low leakage op amp and polystyrene capacitors to hold the voltage (and of course a very long reference PLL time constant), or some sort of sample and hold circuit. Not knowing your system requirements, this may or not be feasible, but it would be my first try at a solution.

Added after 4 minutes:

Also, the type of pll chip that you use is very important. I have, unfortunately, learned that most of the "fractional N" pll chips are very unforgiving of any sort of disruption, no matter how brief, of the reference clock! Something goes haywire inside of the fractional part of the chip that requires many reference clock pulses to reset, often forcing a huge jump in VCO frequency as the "event" occurs.

 

[Danielye]

pll static phase error definition

I want to use EPLD or FPGA to implement the PLL.
Phase detector is a J-K flipflop, and a very high frequency clock is used to counter the pulse from PD. Then the phase error will be quantified.

The digital filter is achieved as loop filter, and it's result feed to the DAC to control the VCXO.

My question is how to design this digital filter to get the zero steady phase error?
Is an ideal integrator just be the thing I have to do?

 

[biff44]

pll clean up loop

You did not say what type of phase error you are trying to eliminate (error from a phase step perturbation, phase ramp, doppler frequency shift, etc). Assuming the simplest case, wanting the steady state phase error to be zero a long time after the a step function pertubation: The key to having a theoretical steady state phase error is to have at least one pure integrator in the loop filter. Here you have a "type 1" system (control theory lingo), where the steady state phase error to a step input is zero.


But things are not that simple. You have a digital system that computes the control voltage needed (with some small truncation error), and feeds that number to a DAC with a finite number of bits of resolution. Inevitably the exact voltage that the VCO needs at any one time will be somewhere between the available two voltages that are one LSB apart. So what will happen is that the phase error will slowly form a sawtooth function, where the phase is too low and the DAC moves up one LSB, and the analog filter in the VCXO ramps up the oscillator's phase vs time. Eventually the phase of the VCXO will become too high, and the DAC will move down one LSB, and the analog filter will ramp the VCXO phase down vs time. This will happen over and over forever, along with any noise perturbations that the pll is trying to clean up.

So 95% of the phase error can be cleaned up with using at least one integrator in the loop filter (the integrator can be arithmetical, like a up/down register, etc). The other 5% will be quantization error.

At higher frequencies, there may be some gate delay variations, transmission line distances, etc, that also add small steady state errors to even a type one system.