Danielye
Junior Member level 3
pll phase error
In classic PLL theory, the steay phase error depends on the loop gain(K),and initial frequecy error(Δf). However,could the steady phase error of the PLL be settable by ourselves?
If I want the steady phase error to be 100us after locked, that is, the time offset between the rising edge of input reference and that of feedback signal divided from VCO,
How to design the architecture of the PLL.
Thanks in advance!
In classic PLL theory, the steay phase error depends on the loop gain(K),and initial frequecy error(Δf). However,could the steady phase error of the PLL be settable by ourselves?
If I want the steady phase error to be 100us after locked, that is, the time offset between the rising edge of input reference and that of feedback signal divided from VCO,
How to design the architecture of the PLL.
Thanks in advance!