How to implement a Phase detector with 1ns resolution

[Danielye]

prs10m.pdf

How to implement a PD for the DPLL using the time-tagging method with 1ns resolution?
I think there must be circuit to expand the phase error pulse and then sampling it with high freq. clock.
could someone kindly give me some help on how to design this circuit? Thanks in advance!

 

[greenfrog]

sonsivri

this is hard, will you design a board-level circuit or an integrated circuit? if it is board-lveel, i donot think there is a practical way of doing that.

 

[biff44]

Could you be a little more specific. We would need to know your application in detail and what you mean by" 1 nS". By nature, many analog or digital phase detectors have sub nano-second resolution. Use one of them.

People use time tagging in signal distribution systems, like at Cern. The Very Large Array (VLA) for astronomy distributes high purity signals also. There are many design considerations, especially noise in the fiberoptic distribution system.

icalepcs2003.postech.ac.kr/Proceedings/PAPERS/MP533.PDF

Also, it is possible to build time interval to voltage converter circuits with 0.3 nS resolution.

 

[ddt694]

Hi, dear biff44

I am interesting in this topic too. The time tagging phase detector may be like this:

www.thinksrs.com/downloads/PDFs/Manuals/PRS10m.pdf --pp14

 

[biff44]

I don't see it. What page? That pdf file is for a rubidium source. It frequency locks an ocsillator by means of an optical qenching effect in Rubidium gas by using a differentiating circuit. I do not see the relavance to time tagging.

 

[ddt694]

Hi, Biff44
Please see the figure-3 of the prs10m.pdf in page 15.

the following is from page 14 of the prs10m.pdf

The PRS10 may be locked to an external 1pps source. A second
order digital PLL is used to adjust the frequency of the PRS10 to match the
frequency of the 1pps source over long time intervals.

The phase detector is the time-tagging circuit and firmware, which has a gain of Kdet = 1bit/ns. The loop filter is a digital filter
consisting of an optional pre-filter and a standard proportional-integral controller

 

[Danielye]

If 1ns/bit resolution of phase comparator was achieved in classical method, it require a counter with 1GHz sampling clock.

So, with classical phase detector, such as JK flipflop, we can get a phase error pulse. Then, After proportionally expanding the width of the pulse with a integral cuicuit, the high resultion phase detector by low frequency clock may be implemented.

I am seeking a appropriate pulse expanding cuicuit now. Could you give me some suggestions? Thanks!