Danielye
Junior Member level 3
prs10m.pdf
How to implement a PD for the DPLL using the time-tagging method with 1ns resolution?
I think there must be circuit to expand the phase error pulse and then sampling it with high freq. clock.
could someone kindly give me some help on how to design this circuit? Thanks in advance!
How to implement a PD for the DPLL using the time-tagging method with 1ns resolution?
I think there must be circuit to expand the phase error pulse and then sampling it with high freq. clock.
could someone kindly give me some help on how to design this circuit? Thanks in advance!