how to implement the JK flipflop->edge control phase dete

[Danielye]

How to implement this logic in VHDL
the logic table is as follows,

K J out
H/L rise edge H
rise edge H/L L
H/L fall edge No change
fall edge H/L No change

Thanks in advance!

 

[adap]

What do you mean by rise edge H and rise edge H/L? Is it the clock?

 

[tongson]

clk'event and clk = '1'
j = 1;

clk'event and clk = '0'
k = 1;

 

[Danielye]

Re: how to implement the JK flipflop->edge control phase

How to implement, in VHDL or schematics?
This is use to detect phase of two clock,edge control phase detector,
which is one part of ADPLL.

Logic table: two input, one output

K-------------- J------------ out
H or L ------rise edge------ H
rise edge--- H or L--------- L
H or L ------fall edge ----No change
fall edge--- H or L -------No change

 

[nand_gates]

Re: how to implement the JK flipflop->edge control phase

Here it goes!! This one is quite common!!! But I dont know will it really work or
not. The FFs may go metastable!!

library ieee;
use ieee.std_logic_1164.all;
entity phase_detect is
  
  port (
    J : in  std_logic;
    K : in  std_logic;
    Q : out std_logic);

end phase_detect;

architecture behave of phase_detect is
signal Q1,Q2 : std_logic;
signal reset : std_logic;
begin  -- behave
  reset <= Q1 nand Q2;
  Q <= Q1;
FF1: process (K, reset)
begin  -- process FF1
  if reset = '0' then                   -- asynchronous reset (active low)
    Q1 <= '0';
  elsif K'event and K = '1' then        -- rising clock edge
    Q1 <= '1';
  end if;
end process FF1;
  
FF2: process (J, reset)
begin  -- process FF1
  if reset = '0' then                   -- asynchronous reset (active low)
    Q2 <= '0';
  elsif J'event and J = '1' then        -- rising clock edge
    Q2 <= '1';
  end if;
end process FF2;

end behave;

Hope this helps....

 

[Danielye]

Re: how to implement the JK flipflop->edge control phase

It does work! Thank your very much!

 

[bazook]

I know this is really old thread but @nand_gates's code doesn't work good in my opinion. Follow the Best book about ADPLL I found that there is no error when signals J and K have opposite phase. Then result is square wave like J input. My simulation shows this unfortunatelly:


So I tried to design my own and now I have this:

library ieee;
use ieee.std_logic_1164.all;
entity phase_detect is
  
  port (
    J : in  std_logic;
    K : in  std_logic;
    Q : out std_logic);

end phase_detect;

architecture behave of phase_detect is

signal JJ : std_logic := '0';
signal KK : std_logic := '0';
begin

	Q 	<=  	'0' when K='1' and KK='0' else 
				'1' when J='1' and JJ='0';
	KK <= 	'1' when K='1' and KK='0' else
				'0' when K='0';
	JJ <= 	'1' when J='1' and JJ='0' else
				'0' when J='0';

end behave;

I couldn't use twice: rising_edge so I had to use this way. It works in simulation but I have 3 warnings:
WARNING:Xst:737 - Found 1-bit latch for signal <JJ>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <KK>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <Q>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.

My qustion: is it a problem?