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I can see you have almost 40 dB of variation over MC runs.. it seems quite strange, in differential mode. And the rejection of your common mode is really poor. You should check your design, especially OP over different runs. Are you adding only mismatch variations or also process variations?
Chopper switches are critical from the charge injection and residual offset point of view.
First, symmetry is critical. You should maintain an exact symmetry between each path of the chopper switches. Second, you should minimize parasitic capacitance from drain to gate. You can use a shielding...
I am not sure about your problem.
But the output bitrate should be defined by your oversampling ratio i think. Then, your clock will be given by this frequency.
I would also like to add that a SC also performs sample and hold by itself. So the switch frequency is the SH freq.
Hi all,
I designed a custom phase generator via Schematic Editor. Due to large number of ports, i use Encounter to do routing.
This is the flow:
1)schematic editor with IO pins and INOUT pins vdd and gnd
2)export Verilog netlist via Verilog XL
3) import design into Encounter with all the...
Hi,
i was wondering if a worst case phase margin of 40 degrees can be enough for a CMFB in a fully differential amplifier. Due to topology, it is not easy to increase it furtherly. Transient response shows only very limited ringing in response to step on the CM reference.
Then, how could it be...
Re: Interdigitation layout
i think both are ok but if it is a current mirror the first one allows you to share S and D diffusions and save area. In the 2nd case, it seems you have to draw each MOST in its own active
I have a question about layout.
I have performed the layout of accurate mos switches. I connected directly D and S with metal2 putting some vias on the D and S metal1 contact.
Can this cause some sort of problem for matching?
Maybe the CGD can be increased due to the parasitic cap from metal2...
ok but i was just talking about the voltages of the cascode MOSTs. However, i found the proper way to do it to obtain acceptable robustness over T and corners. Thank you for your valuable help.
ok, i will try to evaluate a PTAT biasing and see if it helps. However, being it a test chip, the idea was to bias it from an external source, with a fixed and well known current.
thanks for the clarification. I also have some trouble in this mixed corner, due to how the complete circuit is...
Hi all,
I am trying to design a biasing network for a gain boosted folded cascode (1.8V), able to work in all corner at room T, and able to work in a decent way also at -40 and 200 C. I assume constant reference current (external source).
At this point, i used simple diode-connected MOS with a...
eps0 is the air dielectric constant and epsSiO2 is the dielectric constant of the silicon dioxide. They are physical quantities.
The u0 value that you have calculated in this way does not take into account mobility degeneration due to vertical and horizontal biasing, so expect that your...
SPICE requires a node 0 to write the netlist, which is given by the (global) gnd. It is a convention, only a reference. All the voltages in the reality have sense only as "difference" from one node potential to another.
and more, the latch up is basically a SCR circuit. If it turns on, it runs fastly to an increasing current due to positive feedback casuing malfunctioning or even destruction
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