problem with vdd and gnd connection in extracted netlist

[Braski]

Hi all,

I designed a custom phase generator via Schematic Editor. Due to large number of ports, i use Encounter to do routing.

This is the flow:
1)schematic editor with IO pins and INOUT pins vdd and gnd
2)export Verilog netlist via Verilog XL
3) import design into Encounter with all the necessary
4) do all p&R steps using vdd and gnd as power nets
5) extract the gds2 and final verilog netlist from Encounter
6) stream in into Virtuoso
7)add vdd and gnd pins to layout
8)DRC
9)LVS vs verilog netlist imported as a schematic

when it comes to extract the final verilog netlist, Encounter does not add vdd and gnd connections to the instances it added, like decaps or buffers for clock tree. If i do connect them by hand, LVS is almost fine (only a DK related problem with decap parameters)

It is boring. Where am i doing a mistake? I think i made some mess with vdd and gnd net. But where?

 

[vijayR15]

Hai braksi,

Have u done global net connection in encounter.. If not use the below command

globalNetConnect vdd -type pgpin -pin vdd
globalNetConnect gnd -type pgpin -pin gnd

Also do special route

 

[Braski]

I have not done global net connections because vdd and gnd are not instantiated as global nets in the netlist. Should i do it the same?

 

[vijayR15]

Try with this.. so that supply will easily spread over to all rails..


may be it helps.


without mentioning as global.. we can also clean lvs for a block if it has vdd and vss as a pin connection..

Make sure ur power pin connections have correct names ex:- vdd as vdd not as vdd1