question about layout: connecting D and S directly

[Braski]

I have a question about layout.

I have performed the layout of accurate mos switches. I connected directly D and S with metal2 putting some vias on the D and S metal1 contact.
Can this cause some sort of problem for matching?
Maybe the CGD can be increased due to the parasitic cap from metal2 to poly (Fringe effect?) ? This can impact charge injection...

 

[D.A.(Tony)Stewart]

Discrete MOS are notorious mismatched unless they come from the same wafer.

 

[Braski]

how could you figure out i was talking of discrete MOS when i wrote VIAS, metal1, contact, metal2-poly parasitics?

 

[dick_freebird]

You could quantify the likely contribution if you wanted to dig
into the models and calculate the various parasitic capacitances,
but my preference is just to lay things out for physical symmetry
in every respect - even running "useless" stubs on a line from
contacted FETs over ones it doesn't.

I would not expect matching of any quality in a NMOS/PMOS
pair switch, there are too many non-common variables there.

 

[dgnani]

I have a question about layout.

I have performed the layout of accurate mos switches. I connected directly D and S with metal2 putting some vias on the D and S metal1 contact.
Can this cause some sort of problem for matching?
Maybe the CGD can be increased due to the parasitic cap from metal2 to poly (Fringe effect?) ? This can impact charge injection...

The usual general considerations apply if you are seeking matching of CMOS switches but we could help more if you were to mention the process you are using and the context (e.g are all switches connected to the same reference?).
In general:
- keep NFET of separate switches close to each other and with the same orientation
- same for PFETs
- make the switch areas as big as possible
- use interleaving and common centroid techniques
- build a single layout cell and bring all pins to the edges of the cell (even if the extractor might not be accurate -depending on rule implementation- when you use adjacent metal over a pcell, you will at least preserve matching)

Reply if you want more specific considerations

 

[D.A.(Tony)Stewart]

Forgive my ignorance in overlooking the metal1 reference designation info, I forgot recent designs of CMOS and MOSFETS actually have metal contacts instead of the oxide layer for getting improved performance. In either case, matching with fringe and crosstalk effects is still tricky.