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french equivalent of sva
Hello all,
my verilog testbench has a global variable that counts the number of errors during a simulation. Every time an error is detected during the simulation the global variable gets incremented. At the end of the simulation, the testbench checks this variable to...
Hi all,
what's the trick to perform 9 bit arithmetics in C? I am modeling a hardware design and I need to perform signed 9bit arith with saturation.
Any ideas??
Cheers
Re: clock dividers
To divide by 2 you can simply use a toggle flop.
In other words you connect the QN output to the D input of the flop. The Q output will toggle with half the frequency of the clock you connect to the CLK port of that flop.
Dear all,
how would you check that a clock is actually running using verilog?
How would you check that this same clock has changed its polarity??
Your help is appreciated and of course recognized.
cheers!
Dear all,
I have a piece of code that describes a 13-bit flip-flop being reset to a 10-bit pattern:
reg [`MSB20:0] reg20;
always @(posedge clk or negedge rstb_regs)
if (~rstb_regs)
reg20 <= 10'b00_1000_0000;
else
......
In simulation I see that bits 13:10 are reset to zero.
But what...
Hello,
I am filtering a test signal (Tsig) with a FIR and then calculating the
RMS error against a reference signal (Ref).
The FIR adds a group delay to my test signal which needs to be compensated
before I can calculate the error.
For an FIR, I believe that delay compensation should be N/2...
low pass filter response for ramp signal
Hello,
could you guys please give me an explanation why if I low pass filter an upsampled (zero stuffed) ramp signal I get some oscillation which increases in amplitude with time?
The time frame that I am looking is very big in comparison to the...
Hi,
C/C++ is surely one of the most used languages for hardware verification. Either for testbench code or for reference modeling. In both cases integrated to the logic simulator through a DPI/PLI/FLI interface or a SystemC shell.
In processor driven testbenches where verification engineers...
Re: what is delay cell ?
Usually you have a set of delay cells with different delay values, they are all footprint compatible (same dimensions), This compatibility facilitates timing adjustments because you can freely change any delay cells you use at a given point in the circuit.
They have...
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