uncomplete reset assignmet to reg, What happens in Synth???

[Arturi]

Dear all,

I have a piece of code that describes a 13-bit flip-flop being reset to a 10-bit pattern:

reg [`MSB20:0] reg20;

always @(posedge clk or negedge rstb_regs)
if (~rstb_regs)
reg20 <= 10'b00_1000_0000;
else
......

In simulation I see that bits 13:10 are reset to zero.

But what happens in synthesis??? Do the most significant register are synthesized to flops with asynchronous reset?? Or the tool chooses plain flops which have less area?? After all we are not specifying a reset value for these flops...

Thanks,

Arturi

 

[iwpia50s]

13:10 are synthesized to DFF with reset and 9:0 are synthesized to DFF wothout reset.

 

[shiv_emf]

Can we expect latches in here?

 

[iwpia50s]

Probably, since they are outside the always block.

 

[pranam.bhagavan]

Re: uncomplete reset assignmet to reg, What happens in Synth

Dear all,

I have a piece of code that describes a 13-bit flip-flop being reset to a 10-bit pattern:

reg [`MSB20:0] reg20;

always @(posedge clk or negedge rstb_regs)
if (~rstb_regs)
reg20 <= 10'b00_1000_0000;
else
......

In simulation I see that bits 13:10 are reset to zero.

But what happens in synthesis??? Do the most significant register are synthesized to flops with asynchronous reset?? Or the tool chooses plain flops which have less area?? After all we are not specifying a reset value for these flops...

Thanks,

Arturi

All FF's will have SET/RESET pin depend upon '1' or '0'. Since you say only 10'b... it will append zeros to MSB. So it will be reset for FF 12:10.