n1cm0c
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I'm doing full custom analog blocks which need some simple FSM digital blocks.
Our digital people are too busy using Synopsys/Cadence/Mentor latest generation tools to design huge digital ASICs in nanometer technologies, so there's no-one to help me write VHDL/Verilog synthetisable code and use these tools to generate a SPICE/Spectre/Hspice netlist that I can use to simulate my full circuit (98% analog, 2% digital).
I know I could use VHDL-AMS or Verilog-AMS to model everything together, but I think this is overkill, since the digital part is so small. My simulations will take longer, I'll need more expensive licenses, and probably also learn a "new" language (the -AMS).
In the final phase of my design the digital part will be synthetised by the digital experts, and then I'll get back the full SPICE netlist with all parasitics, etc.
But before I get there I'd like to be able to synthetise my FSMs, using some simple, low-cost and easy to use tool, so that I could have SPICE netlists of the digital part I could use in my simulations. I have a library of digital standard cells with full layout, and SPICE netlists for them, and I'd like to synthetise logic using that library.
I am looking for something similar to the berkeley tools (octtools, msii, mvsis, sis, whatever), but commercial (with some support), and able to take RTL VHDL as input. Maybe something like Exemplar Logic? Many years ago I recall using something like that, I think.
So, my question to you digital experts is: Could you suggest an ASIC logic synthesis tool that accepts RTL VHDL and outputs a gate level netlist (against a standard cell library), preferably in SPICE/HSPICE/SPECTRE syntax ?
Thanks for any help!
Our digital people are too busy using Synopsys/Cadence/Mentor latest generation tools to design huge digital ASICs in nanometer technologies, so there's no-one to help me write VHDL/Verilog synthetisable code and use these tools to generate a SPICE/Spectre/Hspice netlist that I can use to simulate my full circuit (98% analog, 2% digital).
I know I could use VHDL-AMS or Verilog-AMS to model everything together, but I think this is overkill, since the digital part is so small. My simulations will take longer, I'll need more expensive licenses, and probably also learn a "new" language (the -AMS).
In the final phase of my design the digital part will be synthetised by the digital experts, and then I'll get back the full SPICE netlist with all parasitics, etc.
But before I get there I'd like to be able to synthetise my FSMs, using some simple, low-cost and easy to use tool, so that I could have SPICE netlists of the digital part I could use in my simulations. I have a library of digital standard cells with full layout, and SPICE netlists for them, and I'd like to synthetise logic using that library.
I am looking for something similar to the berkeley tools (octtools, msii, mvsis, sis, whatever), but commercial (with some support), and able to take RTL VHDL as input. Maybe something like Exemplar Logic? Many years ago I recall using something like that, I think.
So, my question to you digital experts is: Could you suggest an ASIC logic synthesis tool that accepts RTL VHDL and outputs a gate level netlist (against a standard cell library), preferably in SPICE/HSPICE/SPECTRE syntax ?
Thanks for any help!