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Recent content by abhiverma812

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    Full, empty detection in fifo design

    There are 2 ways to design synchronous FIFO that I know: 1. Using n+1 bit counters for write pointer and read pointer. In this case, since it is 8 location FIFO, you can use 3+1 = 4 bit counter. To detect full and empty is simple: FULL: WP-RP = 4'b1000 EMPTY: WP-RP=4'b0000 We cannot decide...
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    Readjusting position of cells to fix set up

    Can you elaborate the question??
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    How does multicycle path arise at CDC even when we use asynchronous fifo?

    Since there are 2 clocks and data is transferred between producer and consumer, hence we say that paths between async FIFO are CDC paths. In facts, to resolve CDC issues we add FIFO in the design. Once FIFO is in design, we generally tell STA tool (like primetime) that these paths are FIFO...
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    Order of preference of serving false path and multicycle path

    Hey, False path constraint is much more strict, as you are saying that paths between launching and capturing flip flops will not exist, may be due to some architectural condition. Hence, tool will not time those paths. I guess SCP is single cycle paths. I am not sure about SMT. Thanks, Abhishek
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    Hold Check in Multi cycle path

    Well if you know the answer I will appreciate if you can post it here. It will be helpful. I know the difference between setup and hold. Thanks, Abhishek
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    vcs equivalent of modelsims log -r ?

    Hey, I guess you just need to give -fsdb or -vpd switch while you are running VCS. Then you can open the GUi and add any signal you want. Thanks, Abhishek
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    Hold Check in Multi cycle path

    Hey experts, I have a question related to Multi cycle paths. I know that by default, the hold is always checked one clock edge prior to setup edge. Also during MCO exceptions, we add hold constraints where we move hold checking to different edges. Can anyone explain: 1. why hold checks are...
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    NMOS pass characteristics

    Well width and length does not matter in this case and you can never go beyond Vdd-Vtn. You need to understand the working of NMOS and various regions it can work in. For NMOS to pass current and act as switch, a minimum difference in voltage of Vtn should exist between gate and source, i.e. Vgs...
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    Split Cache Implementation

    Hey, I am trying to implement a split cache simulator. My main aim is to separate clean cache and dirty cache. However, for caches we need the size must be power of 2. Lets say unified cache is 64k. Now I can split it as (say) 8k and 56k or any other configuration. My question is how to deal...
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    Interview question - Migrating to smaller technology.

    Hey, I guess when you are talking about technology scaling down, you are talking about pre-chip fabrication. I am not too sure if we can use a chip with older technology with new scaled down technology. However, I think there must be some mechanism in which you can provide backward...
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    Relationship between power and parallelism.

    Hello experts, I was curious to know how power (dynamic and static) are related to number of cores (parallelism) in CPU design. I read somewhere that dynamic power favors multi-processing while static power favors uni-processing. However, I was not able to understand it. Can someone throw...
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    [FIFO] Almost-Full/Almost-Empty - why needed?

    Hey, I will divide the answer into 2 parts, synchronous and asynchronous FIFOs. Synchronous FIFO: This is the case where both producer and consumer are working on same clock frequency. Consider the EMPTY condition in a 8 location FIFO. Write pointer (WP) and read pointer (RP) are at same...
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    FIFO with simultaneous R/W - best implementation

    @qieda Hello, I am curious about this question. I didn't really understood your 2nd answer. Do you mean that we are writing on positive edge and reading on negative edge of the clock.? Is it possible.? Abhishek
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    how to practice verilog.

    Hi, As already told here, use Modelsim for start. You can download student version license from model.com. In case you need to practice, I can give you some small projects to work on. Ping me if you need help. Apart from this try ASIC world for learning the language. Best Regards, Abhishek
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    Synthesis mean only Conversion?

    Hey, Synthesis is not just converting RTL or higher level design into lower level (mainly gate level). Synthesis tools like synopsys design compiler also do optimization of your design. There are various algorithms which are followed based on the design and constraints put by the designer. This...
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