1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    107,101
Page 3 of 742 FirstFirst 1 2 3 4 5 13 53 103 503 ... LastLast
Threads 61 to 90 of 22244

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. if statement within a generate for loop

    Started by jasmine123, 12th April 2018 07:47
    • Replies: 7
    • Views: 530
    13th April 2018, 03:19 Go to last post
  2. setup violation in physical designing

    Started by vinu114, 12th April 2018 07:05
    • Replies: 3
    • Views: 343
    13th April 2018, 01:44 Go to last post
    • Replies: 8
    • Views: 849
    12th April 2018, 10:00 Go to last post
  3. Timing constraints for clock domain crossing

    Started by urbanzrim, 10th April 2018 07:31
    • Replies: 6
    • Views: 571
    12th April 2018, 05:45 Go to last post
  4. Is logic cell a technology independent parameter

    Started by rafimiet, 11th April 2018 09:58
    • Replies: 7
    • Views: 573
    12th April 2018, 04:51 Go to last post
  5. Simulating Xilinx smpte sdi core

    Started by paulr127, 10th April 2018 12:04
    • Replies: 8
    • Views: 664
    11th April 2018, 15:12 Go to last post
  6. Kintex Transceiver bank configuration

    Started by beginner_EDA, 11th April 2018 13:39
    • Replies: 0
    • Views: 301
    11th April 2018, 13:39 Go to last post
  7. Output pixel larger than the desired pixel

    Started by fatimamaz, 27th March 2018 13:04
    • Replies: 3
    • Views: 580
    10th April 2018, 10:21 Go to last post
  8. [SOLVED] Verilog error , Pls help

    Started by abimann, 16th March 2018 16:31
    • Replies: 13
    • Views: 1,386
    10th April 2018, 02:29 Go to last post
  9. Assignment of DSP Slices in FPGA

    Started by expertengr, 6th April 2018 10:07
    • Replies: 5
    • Views: 525
    9th April 2018, 18:47 Go to last post
    • Replies: 3
    • Views: 456
    9th April 2018, 14:24 Go to last post
  10. RF/IF signal recorder board

    Started by ali_th, 9th April 2018 05:04
    • Replies: 2
    • Views: 314
    9th April 2018, 12:08 Go to last post
  11. hd-sdi interface testing

    Started by paulr127, 6th April 2018 13:41
    • Replies: 9
    • Views: 752
    8th April 2018, 11:53 Go to last post
  12. Techniques to solve metastability issue in VHDL

    Started by expertengr, 6th April 2018 10:17
    • Replies: 14
    • Views: 868
    7th April 2018, 06:59 Go to last post
    • Replies: 0
    • Views: 267
    6th April 2018, 12:06 Go to last post
  13. Need logic that implement in Verilog coding

    Started by tayyab786, 6th April 2018 08:32
    • Replies: 0
    • Views: 261
    6th April 2018, 08:32 Go to last post
  14. declaring a constant value for all modules in verilog

    Started by dipin, 6th April 2018 06:12
    • Replies: 3
    • Views: 327
    6th April 2018, 07:39 Go to last post
  15. Usage of HP and HR IO banks and their selection

    Started by Alauddin123, 5th April 2018 06:54
    • Replies: 1
    • Views: 378
    5th April 2018, 07:29 Go to last post
  16. 12 Hour Clock using VHDL

    Started by triplel06, 3rd April 2018 01:12
    • Replies: 8
    • Views: 793
    4th April 2018, 16:59 Go to last post
  17. [MOVED] Need Verilog code for Ethernet protocol

    Started by mhafdhia, 4th April 2018 01:30
    • Replies: 2
    • Views: 459
    4th April 2018, 08:52 Go to last post
  18. Interfacing a buzzer with CPLD

    Started by garvind25, 25th March 2018 16:56
    • Replies: 9
    • Views: 763
    3rd April 2018, 18:45 Go to last post
  19. Concurrent constructs in Verilog?

    Started by samg, 2nd April 2018 10:56
    • Replies: 2
    • Views: 363
    3rd April 2018, 10:18 Go to last post
  20. copying a file from fpga to pc without modem

    Started by dipin, 30th March 2018 15:45
    • Replies: 2
    • Views: 428
    1st April 2018, 22:43 Go to last post
  21. Converting an array of std_logic to string

    Started by shaiko, 30th March 2018 11:45
    • Replies: 9
    • Views: 780
    30th March 2018, 23:16 Go to last post
  22. AXI4 stream bus and arbitration

    Started by filip.amator, 30th March 2018 22:47
    • Replies: 0
    • Views: 344
    30th March 2018, 22:47 Go to last post
  23. Queries on JTAG interface for a CPLD based system

    Started by garvind25, 10th March 2018 18:31
    • Replies: 7
    • Views: 737
    29th March 2018, 11:36 Go to last post
    • Replies: 10
    • Views: 958
    28th March 2018, 14:02 Go to last post
  24. Overflow pointer cell

    Started by nsgil85, 27th March 2018 17:09
    • Replies: 3
    • Views: 406
    28th March 2018, 11:17 Go to last post