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Threads 61 to 90 of 22390

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Code Coverage and Functional Coverage

    Started by M.Mata, 10th August 2018 19:50
    • Replies: 5
    • Views: 482
    18th August 2018, 22:19 Go to last post
  2. HDL vs Software Mentalities

    Started by redsees, 15th August 2018 15:58
    2 Pages
    1 2
    • Replies: 21
    • Views: 909
    18th August 2018, 01:05 Go to last post
    • Replies: 2
    • Views: 186
    16th August 2018, 20:32 Go to last post
  3. Closed: FPGA to eMMC clk frequency & adjustable sampling point

    Started by wesleytaylor, 1st November 2017 11:49
    • Replies: 1
    • Views: 739
    14th August 2018, 15:49 Go to last post
    • Replies: 5
    • Views: 231
    14th August 2018, 14:11 Go to last post
  4. Problems in the I2C master

    Started by PablodlR, 8th August 2018 11:32
    • Replies: 9
    • Views: 478
    13th August 2018, 14:51 Go to last post
  5. Weird synthesis error (Xilinx, Verilog)

    Started by dayana42200, 13th August 2018 01:58
    • Replies: 4
    • Views: 399
    13th August 2018, 09:58 Go to last post
  6. In-Circuit Emulators

    Started by M.Mata, 10th August 2018 19:37
    • Replies: 1
    • Views: 138
    10th August 2018, 20:54 Go to last post
  7. ISE xc2c64a, 2 output, phase.

    Started by victor910, 7th August 2018 04:22
    2 Pages
    1 2
    • Replies: 30
    • Views: 999
    10th August 2018, 09:50 Go to last post
  8. how to calculate exponential (fixpoint) in fpga?

    Started by jalal.baba, 9th August 2018 10:46
    • Replies: 6
    • Views: 302
    9th August 2018, 16:07 Go to last post
  9. How to do fractional downsampling using Lagrange?

    Started by bravoegg, 9th August 2018 08:19
    • Replies: 1
    • Views: 151
    9th August 2018, 13:14 Go to last post
  10. [SOLVED] Xilinx fft core output not proper

    Started by Radhikamkr, 8th August 2018 11:07
    • Replies: 1
    • Views: 220
    8th August 2018, 13:56 Go to last post
  11. Multiplication of float/real value in VHDL

    Started by arunprasadvr3, 8th August 2018 08:59
    • Replies: 8
    • Views: 327
    8th August 2018, 11:00 Go to last post
    • Replies: 6
    • Views: 502
    7th August 2018, 11:01 Go to last post
  12. Problem understanding System Verilog

    Started by redtomato11, 1st July 2018 21:38
    • Replies: 3
    • Views: 421
    7th August 2018, 04:51 Go to last post
  13. Xilinix to Quartus "Library Conversion"

    Started by UmarKhayyam, 26th July 2018 15:13
    • Replies: 1
    • Views: 206
    5th August 2018, 13:46 Go to last post
  14. register settings for BMP280

    Started by abimann, 4th August 2018 10:22
    • Replies: 1
    • Views: 184
    4th August 2018, 10:56 Go to last post
  15. VHDL sigma delta adc code

    Started by david94, 28th July 2018 14:00
    • Replies: 1
    • Views: 358
    3rd August 2018, 18:00 Go to last post
    • Replies: 8
    • Views: 490
    3rd August 2018, 12:09 Go to last post
    • Replies: 4
    • Views: 460
    2nd August 2018, 15:55 Go to last post
  16. "Evaluation boards" versus "Production boards"

    Started by FlyingDutch, 1st August 2018 09:39
    • Replies: 3
    • Views: 265
    1st August 2018, 16:49 Go to last post
  17. OpenCL host code in Vivado

    Started by arishsu, 30th July 2018 03:27
    • Replies: 2
    • Views: 231
    31st July 2018, 23:24 Go to last post
  18. [SOLVED] Force fitting block without drive output

    Started by nsgil85, 12th July 2018 09:23
    • Replies: 2
    • Views: 300
    28th July 2018, 21:35 Go to last post
  19. I2C Clock not generated by master....

    Started by velu.plg, 27th July 2018 19:40
    • Replies: 3
    • Views: 307
    28th July 2018, 12:32 Go to last post
  20. procedure of PROCESS in VHDL

    Started by kahroba92, 26th July 2018 15:41
    2 Pages
    1 2
    • Replies: 22
    • Views: 892
    27th July 2018, 19:20 Go to last post
  21. Sending data from dev/mem using mmap to PL side

    Started by dipin, 27th July 2018 07:46
    • Replies: 0
    • Views: 196
    27th July 2018, 07:46 Go to last post
  22. Learning HW design with FPGA

    Started by vishnuk, 20th July 2018 06:51
    • Replies: 9
    • Views: 661
    26th July 2018, 20:53 Go to last post