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Threads 61 to 90 of 22761

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] VHDL scope vs visibility vs visibility by selection

    Started by wesleytaylor, 10th September 2019 09:23
    • Replies: 3
    • Views: 268
    10th September 2019, 16:16 Go to last post
  2. [SOLVED] problem with programming the xilinx fpga

    Started by hamidkavianathar, 25th August 2019 13:23
    • Replies: 4
    • Views: 849
    8th September 2019, 13:23 Go to last post
    • Replies: 2
    • Views: 452
    7th September 2019, 09:49 Go to last post
  3. CDC - How make merge data after conversion?

    Started by arkadyy, 5th September 2019 13:25
    • Replies: 10
    • Views: 626
    6th September 2019, 22:15 Go to last post
  4. Sine function generator (VHDL)

    Started by FlyingDutch, 11th August 2019 15:33
    • Replies: 6
    • Views: 742
    5th September 2019, 17:35 Go to last post
  5. Inferred VHDL dual port RAM template

    Started by shaiko, 30th August 2019 00:01
    • Replies: 7
    • Views: 594
    5th September 2019, 11:56 Go to last post
  6. ERROR:HDLParsers:709

    Started by abimann, 4th September 2019 08:05
    • Replies: 2
    • Views: 334
    4th September 2019, 09:04 Go to last post
  7. HELP ME the newbie with Verilog Code

    Started by ridhohrnf, 3rd September 2019 18:07
    • Replies: 3
    • Views: 308
    4th September 2019, 08:28 Go to last post
    • Replies: 12
    • Views: 1,306
    3rd September 2019, 15:48 Go to last post
  8. pcie hard ip altera- latency problem

    Started by manush30, 3rd September 2019 09:04
    • Replies: 3
    • Views: 463
    3rd September 2019, 13:26 Go to last post
  9. Switching between more bit-streams on FPGA

    Started by MSAKARIM, 29th August 2019 20:58
    • Replies: 2
    • Views: 569
    1st September 2019, 14:40 Go to last post
  10. [SOLVED] VHDL: reading text file stops at endfile()

    Started by igaco, 30th August 2019 22:25
    • Replies: 3
    • Views: 430
    31st August 2019, 11:46 Go to last post
  11. Req: Bluspec Systemverilog good learning materials

    Started by Zerox100, 27th August 2019 11:49
    • Replies: 1
    • Views: 354
    30th August 2019, 18:12 Go to last post
  12. Shifting control from one module to another iteratively

    Started by rrucha, 28th August 2019 22:56
    • Replies: 8
    • Views: 619
    30th August 2019, 09:11 Go to last post
  13. SystemVerilog Input generation

    Started by rrucha, 27th August 2019 19:41
    • Replies: 13
    • Views: 787
    30th August 2019, 09:01 Go to last post
  14. Transferring data from PS to PL

    Started by Roronoa137, 19th August 2019 09:48
    • Replies: 8
    • Views: 687
    29th August 2019, 08:18 Go to last post
  15. Lattice FPGAs and Diamond software

    Started by Amadeus, 22nd August 2019 13:37
    • Replies: 5
    • Views: 662
    23rd August 2019, 07:59 Go to last post
  16. Real time voice encryption/decryption with FPGA

    Started by adwnis123, 20th August 2019 19:51
    • Replies: 6
    • Views: 566
    22nd August 2019, 03:11 Go to last post
    • Replies: 5
    • Views: 503
    21st August 2019, 08:42 Go to last post
  17. Introductory literature on PLD

    Started by MikhailFrolov, 20th August 2019 18:51
    • Replies: 4
    • Views: 330
    20th August 2019, 20:52 Go to last post
  18. [SOLVED] How to write in the log file

    Started by Roronoa137, 8th August 2019 07:56
    • Replies: 4
    • Views: 381
    19th August 2019, 09:31 Go to last post
  19. Verilog code for 8 bit register with read/write

    Started by muku383, 14th August 2019 09:54
    • Replies: 6
    • Views: 628
    17th August 2019, 00:29 Go to last post
  20. $urandom for error insertion in Systemverilog

    Started by rrucha, 15th August 2019 21:30
    • Replies: 5
    • Views: 480
    16th August 2019, 19:53 Go to last post
  21. [SOLVED] Comparator gives wrong Output

    Started by padfoot_1729, 16th August 2019 17:45
    • Replies: 1
    • Views: 270
    16th August 2019, 18:02 Go to last post
  22. verilog code using vivado

    Started by sumag, 16th August 2019 08:54
    • Replies: 3
    • Views: 315
    16th August 2019, 15:32 Go to last post
  23. SystemVerilog Assertions into ModelSim

    Started by Fynjisx, 16th August 2019 08:25
    • Replies: 1
    • Views: 243
    16th August 2019, 12:15 Go to last post
  24. [SOLVED] Modelsim clock signal

    Started by maro.pitti, 13th August 2019 18:48
    • Replies: 10
    • Views: 668
    15th August 2019, 17:51 Go to last post
  25. Strategy for a multi signal generator using a MAX10

    Started by Pastel, 11th August 2019 04:05
    • Replies: 10
    • Views: 780
    15th August 2019, 16:45 Go to last post
  26. Embedded Linux Application

    Started by ranayehya, 14th August 2019 19:09
    • Replies: 2
    • Views: 329
    15th August 2019, 08:05 Go to last post