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Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

    • Replies: 7
    • Views: 722
    14th October 2019, 16:56 Go to last post
  1. LTSSM state of PCIe and USR_LNK_UP assertion

    Started by vishnuk, 12th October 2019 11:38
    • Replies: 0
    • Views: 428
    12th October 2019, 11:38 Go to last post
  2. [SOLVED] Reading from a TXT file to a 2d array in vhdl

    Started by yashjain, 2nd October 2019 15:14
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,448
    12th October 2019, 07:32 Go to last post
  3. Implementation of ADC

    Started by student21, 10th October 2019 11:07
    • Replies: 8
    • Views: 1,059
    11th October 2019, 21:39 Go to last post
  4. parameterized MUX implementation

    Started by rrucha, 9th October 2019 00:18
    • Replies: 3
    • Views: 430
    11th October 2019, 20:13 Go to last post
    • Replies: 11
    • Views: 892
    11th October 2019, 16:01 Go to last post
    • Replies: 14
    • Views: 1,084
    10th October 2019, 09:19 Go to last post
  5. Netlist Verilog to RTL or structrual to behavioral

    Started by s002wjhw, 9th October 2019 16:14
    • Replies: 0
    • Views: 249
    9th October 2019, 16:14 Go to last post
  6. Clock Skew problem in oserdes

    Started by beginner_EDA, 8th October 2019 15:31
    • Replies: 1
    • Views: 353
    9th October 2019, 12:23 Go to last post
    • Replies: 4
    • Views: 507
    7th October 2019, 23:12 Go to last post
    • Replies: 2
    • Views: 410
    5th October 2019, 10:14 Go to last post
  7. Testbench input stimulus

    Started by rogger201, 30th September 2019 19:14
    • Replies: 3
    • Views: 489
    4th October 2019, 22:45 Go to last post
    • Replies: 14
    • Views: 935
    4th October 2019, 18:48 Go to last post
  8. Help!! with MUX and Shift Registers in an architecture

    Started by Mai89, 29th September 2019 19:18
    • Replies: 3
    • Views: 426
    4th October 2019, 15:55 Go to last post
    • Replies: 3
    • Views: 571
    4th October 2019, 05:42 Go to last post
  9. Difference between TRN and AXI4-Stream

    Started by buenos, 3rd October 2019 21:37
    • Replies: 2
    • Views: 431
    3rd October 2019, 23:37 Go to last post
    • Replies: 14
    • Views: 1,040
    3rd October 2019, 19:30 Go to last post
  10. Data string length to be send out from FPGA

    Started by Vlad., 2nd October 2019 10:44
    • Replies: 4
    • Views: 476
    2nd October 2019, 17:03 Go to last post
    • Replies: 8
    • Views: 735
    2nd October 2019, 09:49 Go to last post
  11. Ternary Content Addressable memory

    Started by Sisirapk, 1st October 2019 06:49
    • Replies: 2
    • Views: 272
    1st October 2019, 07:42 Go to last post
  12. Simulation about 30MHz -> 1Hz clock divider

    Started by Xilinx_Modelsim, 28th September 2019 08:57
    • Replies: 10
    • Views: 802
    30th September 2019, 23:08 Go to last post
  13. How to declare a variable number of parameters

    Started by pbernardi, 28th September 2019 05:23
    • Replies: 7
    • Views: 595
    30th September 2019, 18:33 Go to last post
  14. UNKNOWN BYPASS problem

    Started by hamidkavianathar, 28th September 2019 15:27
    • Replies: 10
    • Views: 731
    30th September 2019, 08:57 Go to last post
  15. UART TX signalling from another process

    Started by vinodstanur, 29th September 2019 18:07
    • Replies: 1
    • Views: 265
    29th September 2019, 21:19 Go to last post
  16. Help to make use of an .h file in my vhdl code

    Started by Cesar0182, 26th September 2019 17:01
    • Replies: 13
    • Views: 750
    27th September 2019, 21:59 Go to last post
  17. 10 millisecond counter with different frequencies

    Started by tahirsengine, 27th September 2019 08:36
    • Replies: 3
    • Views: 282
    27th September 2019, 09:37 Go to last post
  18. [SOLVED] if else statement inside an always block

    Started by rogger201, 26th September 2019 21:22
    • Replies: 3
    • Views: 327
    26th September 2019, 23:12 Go to last post
  19. Nexys 4 DDR Board UART ERROR

    Started by AvaTRm, 26th September 2019 07:29
    • Replies: 2
    • Views: 295
    26th September 2019, 20:44 Go to last post
  20. [SOLVED] Shift register implementation and use of its value

    Started by rogger201, 23rd September 2019 21:27
    2 Pages
    1 2
    • Replies: 22
    • Views: 996
    26th September 2019, 17:48 Go to last post
  21. MMCM Clocking Wizard

    Started by Roronoa137, 26th September 2019 08:20
    • Replies: 1
    • Views: 259
    26th September 2019, 15:55 Go to last post