1. Announcement:
    Forum rules & policies (quick reference)
    alexan_e (Administrator)
    7th August 2014
    Views:
    125,176
Page 3 of 760 FirstFirst 1 2 3 4 5 13 53 103 503 ... LastLast
Threads 61 to 90 of 22789

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Ternary Content Addressable memory

    Started by Sisirapk, 1st October 2019 06:49
    • Replies: 2
    • Views: 224
    1st October 2019, 07:42 Go to last post
  2. Simulation about 30MHz -> 1Hz clock divider

    Started by Xilinx_Modelsim, 28th September 2019 08:57
    • Replies: 10
    • Views: 712
    30th September 2019, 23:08 Go to last post
  3. How to declare a variable number of parameters

    Started by pbernardi, 28th September 2019 05:23
    • Replies: 7
    • Views: 532
    30th September 2019, 18:33 Go to last post
  4. UNKNOWN BYPASS problem

    Started by hamidkavianathar, 28th September 2019 15:27
    • Replies: 10
    • Views: 623
    30th September 2019, 08:57 Go to last post
  5. UART TX signalling from another process

    Started by vinodstanur, 29th September 2019 18:07
    • Replies: 1
    • Views: 218
    29th September 2019, 21:19 Go to last post
  6. Help to make use of an .h file in my vhdl code

    Started by Cesar0182, 26th September 2019 17:01
    • Replies: 13
    • Views: 664
    27th September 2019, 21:59 Go to last post
  7. 10 millisecond counter with different frequencies

    Started by tahirsengine, 27th September 2019 08:36
    • Replies: 3
    • Views: 239
    27th September 2019, 09:37 Go to last post
  8. [SOLVED] if else statement inside an always block

    Started by rogger201, 26th September 2019 21:22
    • Replies: 3
    • Views: 271
    26th September 2019, 23:12 Go to last post
  9. Nexys 4 DDR Board UART ERROR

    Started by AvaTRm, 26th September 2019 07:29
    • Replies: 2
    • Views: 254
    26th September 2019, 20:44 Go to last post
  10. [SOLVED] Shift register implementation and use of its value

    Started by rogger201, 23rd September 2019 21:27
    2 Pages
    1 2
    • Replies: 22
    • Views: 880
    26th September 2019, 17:48 Go to last post
  11. MMCM Clocking Wizard

    Started by Roronoa137, 26th September 2019 08:20
    • Replies: 1
    • Views: 227
    26th September 2019, 15:55 Go to last post
  12. VHDL integer to integer multiplication

    Started by shaiko, 25th September 2019 11:48
    • Replies: 3
    • Views: 268
    25th September 2019, 13:22 Go to last post
    • Replies: 5
    • Views: 290
    25th September 2019, 13:06 Go to last post
  13. SPI communication in SDK

    Started by Roronoa137, 13th September 2019 14:36
    • Replies: 9
    • Views: 930
    22nd September 2019, 02:05 Go to last post
  14. parameterized insertion of bits to data

    Started by rrucha, 18th September 2019 22:44
    • Replies: 10
    • Views: 684
    21st September 2019, 08:45 Go to last post
  15. Multiplexer output width depends on SELECT

    Started by rrucha, 13th September 2019 18:10
    • Replies: 17
    • Views: 1,120
    20th September 2019, 08:40 Go to last post
    • Replies: 2
    • Views: 292
    18th September 2019, 10:50 Go to last post
  16. [SOLVED] Need help creating Vivado Timing Constraint

    Started by wesleytaylor, 17th September 2019 12:27
    • Replies: 6
    • Views: 407
    17th September 2019, 18:05 Go to last post
  17. [SOLVED] Suppressing the spacing in $fwrite command of Verilog

    Started by tahirsengine, 17th September 2019 09:17
    • Replies: 3
    • Views: 261
    17th September 2019, 15:52 Go to last post
  18. PLDA drivers needed Windows x64

    Started by paradapa, 15th September 2019 12:24
    • Replies: 0
    • Views: 208
    15th September 2019, 12:24 Go to last post
    • Replies: 5
    • Views: 476
    14th September 2019, 06:53 Go to last post
  19. Using calculated CRC as seed for the next CRC calculation

    Started by rrucha, 12th September 2019 00:27
    • Replies: 4
    • Views: 423
    12th September 2019, 22:06 Go to last post
  20. [moved] VHDL of input capture and output compare

    Started by natalfra, 12th September 2019 14:51
    • Replies: 8
    • Views: 452
    12th September 2019, 21:58 Go to last post
    • Replies: 1
    • Views: 153
    12th September 2019, 21:19 Go to last post
    • Replies: 9
    • Views: 774
    12th September 2019, 18:12 Go to last post
  21. Unable to run the simulation correctly ( Modelsim )

    Started by bravo1234, 11th September 2019 08:44
    • Replies: 2
    • Views: 280
    11th September 2019, 16:16 Go to last post
    • Replies: 5
    • Views: 436
    11th September 2019, 12:00 Go to last post
  22. [SOLVED] VHDL scope vs visibility vs visibility by selection

    Started by wesleytaylor, 10th September 2019 09:23
    • Replies: 3
    • Views: 325
    10th September 2019, 16:16 Go to last post
  23. [SOLVED] problem with programming the xilinx fpga

    Started by hamidkavianathar, 25th August 2019 13:23
    • Replies: 4
    • Views: 930
    8th September 2019, 13:23 Go to last post