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Threads 61 to 90 of 22209

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. How to "ARCTAN" Function in VHDL

    Started by Krishna_k, 13th March 2018 10:33
    • Replies: 7
    • Views: 759
    21st March 2018, 19:32 Go to last post
  2. What is the best method for finding adjacency?

    Started by jalal.baba, 20th March 2018 21:24
    • Replies: 0
    • Views: 353
    20th March 2018, 21:24 Go to last post
    • Replies: 5
    • Views: 474
    20th March 2018, 05:44 Go to last post
  3. [moved] ADC in DEO_NANO board

    Started by Chinmaye, 19th March 2018 18:41
    • Replies: 2
    • Views: 347
    19th March 2018, 20:50 Go to last post
    • Replies: 5
    • Views: 545
    19th March 2018, 12:28 Go to last post
  4. Work window is Altera Quartus II software

    Started by vedika, 15th March 2018 05:19
    • Replies: 2
    • Views: 449
    19th March 2018, 10:21 Go to last post
    • Replies: 3
    • Views: 480
    19th March 2018, 10:20 Go to last post
  5. Verilog testbench help!! (bit urgent)

    Started by sonika111, 8th March 2018 14:43
    4 Pages
    1 2 3 ... 4
    • Replies: 62
    • Views: 2,568
    16th March 2018, 16:56 Go to last post
  6. [SOLVED] PCIE PIO example design

    Started by sreevenkjan, 13th March 2018 10:37
    • Replies: 7
    • Views: 609
    16th March 2018, 15:02 Go to last post
  7. .dev library for JED2AHDL

    Started by dk_spb, 16th March 2018 11:08
    • Replies: 0
    • Views: 275
    16th March 2018, 11:53 Go to last post
    • Replies: 8
    • Views: 690
    16th March 2018, 05:55 Go to last post
  8. Shift register bitwidth issue

    Started by promach, 13th March 2018 04:15
    • Replies: 6
    • Views: 644
    15th March 2018, 13:55 Go to last post
    • Replies: 6
    • Views: 551
    15th March 2018, 11:20 Go to last post
    • Replies: 5
    • Views: 490
    15th March 2018, 10:01 Go to last post
  9. [SOLVED] Tracking states of FSM (finite state machine) in Modelsim

    Started by mjuneja, 13th February 2018 10:57
    • Replies: 17
    • Views: 1,578
    15th March 2018, 07:36 Go to last post
  10. VHDL Multiplying by a fraction

    Started by Sofus, 13th March 2018 16:25
    • Replies: 4
    • Views: 456
    13th March 2018, 21:58 Go to last post
  11. What's going on behind FPGA-based Clouds?

    Started by Mohammad Amin Nili, 12th March 2018 13:25
    • Replies: 5
    • Views: 622
    13th March 2018, 21:38 Go to last post
  12. GLS (Timing Simulation) Issue

    Started by varthurravi, 13th March 2018 16:02
    • Replies: 1
    • Views: 246
    13th March 2018, 16:43 Go to last post
  13. A simple question on testbench stimulus

    Started by promach, 7th March 2018 05:12
    • Replies: 16
    • Views: 904
    12th March 2018, 15:04 Go to last post
  14. one clocked process + one combinatorial process

    Started by promach, 12th March 2018 11:52
    • Replies: 3
    • Views: 399
    12th March 2018, 14:10 Go to last post
    • Replies: 3
    • Views: 412
    12th March 2018, 11:54 Go to last post
  15. DDR to AXI INTERFACE.......

    Started by velu.plg, 7th March 2018 06:42
    • Replies: 3
    • Views: 466
    12th March 2018, 09:15 Go to last post
  16. FIFO output is as a Data Packet? Is that possible?

    Started by ram11, 10th March 2018 21:12
    • Replies: 10
    • Views: 602
    12th March 2018, 01:06 Go to last post
  17. problem with floating point ip core xilinx

    Started by jalal.baba, 10th March 2018 18:53
    • Replies: 3
    • Views: 399
    11th March 2018, 10:17 Go to last post
  18. shift_register_compare assert question

    Started by promach, 10th March 2018 15:34
    • Replies: 1
    • Views: 281
    10th March 2018, 18:15 Go to last post
  19. Spartan 6 x Spartan 7 Logic use comparison

    Started by pbernardi, 8th March 2018 14:34
    • Replies: 7
    • Views: 472
    9th March 2018, 14:01 Go to last post
  20. Parameterized bitwidth

    Started by promach, 9th March 2018 08:37
    • Replies: 2
    • Views: 293
    9th March 2018, 09:35 Go to last post
  21. What is mean by hierarchical boundaries ?

    Started by sarang5s5, 8th March 2018 14:08
    • Replies: 0
    • Views: 232
    8th March 2018, 14:08 Go to last post