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Threads 61 to 90 of 22715

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. [SOLVED] "Power" operator with LUT exponent

    Started by clros, 25th July 2019 07:03
    • Replies: 3
    • Views: 417
    25th July 2019, 12:21 Go to last post
  2. Timing and routing to large number of memory banks

    Started by BigKuma, 19th July 2019 23:25
    • Replies: 3
    • Views: 512
    21st July 2019, 06:58 Go to last post
  3. Advanced VHDL book recommendation

    Started by revkarol, 11th July 2019 09:19
    • Replies: 17
    • Views: 1,312
    18th July 2019, 02:28 Go to last post
  4. Hints for pin assignment

    Started by Pastel, 6th July 2019 02:06
    • Replies: 19
    • Views: 1,463
    15th July 2019, 12:47 Go to last post
    • Replies: 1
    • Views: 318
    12th July 2019, 08:43 Go to last post
    • Replies: 6
    • Views: 411
    11th July 2019, 20:25 Go to last post
  5. [SOLVED] FPGA Kit Recommensation

    Started by MSAKARIM, 10th July 2019 14:41
    • Replies: 2
    • Views: 341
    10th July 2019, 16:28 Go to last post
  6. Run python on cyclone 5 soc

    Started by dipin, 20th June 2019 07:50
    • Replies: 4
    • Views: 671
    9th July 2019, 19:14 Go to last post
    • Replies: 5
    • Views: 481
    9th July 2019, 09:37 Go to last post
  7. [SOLVED] vivado post route simulation problem

    Started by sandeep_sggs, 30th June 2019 11:16
    • Replies: 13
    • Views: 1,041
    8th July 2019, 20:32 Go to last post
    • Replies: 15
    • Views: 885
    6th July 2019, 01:57 Go to last post
  8. Connecting FPGA to computer using ft232rl module

    Started by tanish, 4th July 2019 23:47
    • Replies: 0
    • Views: 316
    4th July 2019, 23:47 Go to last post
    • Replies: 10
    • Views: 601
    4th July 2019, 21:41 Go to last post
  9. Asynchronous reset mechanism

    Started by promach, 2nd July 2019 03:51
    • Replies: 14
    • Views: 858
    3rd July 2019, 10:43 Go to last post
  10. How to use array data in Verilog

    Started by Pastel, 2nd July 2019 15:18
    • Replies: 0
    • Views: 266
    2nd July 2019, 15:18 Go to last post
    • Replies: 2
    • Views: 340
    2nd July 2019, 11:56 Go to last post
  11. multiply -ve number and a fraction in verilog

    Started by Chinmaye, 1st July 2019 17:09
    • Replies: 2
    • Views: 290
    1st July 2019, 21:45 Go to last post
    • Replies: 2
    • Views: 317
    29th June 2019, 10:17 Go to last post
  12. Keypad saved number display shift left in Verilog

    Started by cmyang, 28th June 2019 12:08
    • Replies: 4
    • Views: 421
    28th June 2019, 17:26 Go to last post
  13. RS232 Spartan 3E testing

    Started by adwnis123, 27th June 2019 19:17
    • Replies: 2
    • Views: 356
    28th June 2019, 09:08 Go to last post
  14. Avalon MM - using a FIFO with a registered output

    Started by shaiko, 27th June 2019 12:28
    • Replies: 0
    • Views: 246
    27th June 2019, 12:28 Go to last post
  15. OpenCL vs VHDL running in FPGA

    Started by adwnis123, 20th June 2019 13:47
    • Replies: 2
    • Views: 433
    27th June 2019, 12:10 Go to last post
    • Replies: 2
    • Views: 347
    26th June 2019, 13:57 Go to last post
  16. OV7670 camera interface with Digilent SPARTAN 3E

    Started by adwnis123, 19th June 2019 11:48
    • Replies: 9
    • Views: 757
    25th June 2019, 22:58 Go to last post
  17. [SOLVED] verilog set parameter to a module

    Started by beginner_EDA, 20th June 2019 13:12
    • Replies: 1
    • Views: 239
    20th June 2019, 15:55 Go to last post
  18. Use of CPLD/FPGA for a newbie's laser project

    Started by MichelM, 20th June 2019 09:39
    • Replies: 3
    • Views: 345
    20th June 2019, 12:37 Go to last post