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Threads 61 to 90 of 22465

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Request for 3*3 matrix inversion Verilog code

    Started by MVSPAVANKUMAR, 23rd October 2018 10:48
    • Replies: 1
    • Views: 183
    23rd October 2018, 11:03 Go to last post
  2. What is wrong with this Mux code using indexing?

    Started by fouwad, 13th October 2018 22:39
    • Replies: 9
    • Views: 644
    19th October 2018, 07:07 Go to last post
  3. FPGA implimentation of a pulse divider circuit

    Started by jerryvdk, 17th October 2018 10:02
    • Replies: 3
    • Views: 304
    17th October 2018, 13:25 Go to last post
    • Replies: 1
    • Views: 203
    15th October 2018, 22:25 Go to last post
    • Replies: 7
    • Views: 637
    12th October 2018, 15:23 Go to last post
  4. [SOLVED] Design an RTL for different FPGA types compliance

    Started by Mohammad Amin Nili, 10th October 2018 10:17
    • Replies: 4
    • Views: 331
    10th October 2018, 23:52 Go to last post
    • Replies: 8
    • Views: 561
    10th October 2018, 22:17 Go to last post
    • Replies: 0
    • Views: 339
    7th October 2018, 04:16 Go to last post
  5. exponential operator in verilog

    Started by ssrk1050, 4th October 2018 09:52
    • Replies: 11
    • Views: 691
    5th October 2018, 23:14 Go to last post
  6. Warning in Vivado Design Suite during synthesis

    Started by Radhikamkr, 27th August 2018 23:22
    • Replies: 4
    • Views: 849
    3rd October 2018, 17:17 Go to last post
    • Replies: 1
    • Views: 281
    2nd October 2018, 00:05 Go to last post
    • Replies: 7
    • Views: 480
    1st October 2018, 23:22 Go to last post
  7. RIFFA full duplex and multi-threading support

    Started by promach, 7th July 2018 10:16
    • Replies: 15
    • Views: 1,681
    1st October 2018, 11:59 Go to last post
  8. Vivado Combinational Loop DRC

    Started by mselmanerel, 30th September 2018 18:27
    • Replies: 2
    • Views: 230
    30th September 2018, 22:18 Go to last post
    • Replies: 4
    • Views: 344
    29th September 2018, 18:59 Go to last post
  9. Converting a RF signal into baseband using VHDL

    Started by mertberkea, 27th September 2018 09:06
    • Replies: 3
    • Views: 348
    28th September 2018, 16:59 Go to last post
  10. Dual flop synchronizers and mtbf

    Started by Alauddin123, 28th September 2018 11:17
    • Replies: 2
    • Views: 250
    28th September 2018, 14:12 Go to last post
  11. [SOLVED] Comparing ASIC gate-equivalent with Xilinx FPGA LUTs

    Started by dpaul, 27th September 2018 14:42
    • Replies: 4
    • Views: 412
    27th September 2018, 19:38 Go to last post
  12. VHDL substitute text to simplify code.

    Started by buenos, 26th September 2018 02:05
    • Replies: 4
    • Views: 323
    27th September 2018, 08:32 Go to last post
    • Replies: 2
    • Views: 252
    24th September 2018, 22:40 Go to last post
    • Replies: 1
    • Views: 260
    24th September 2018, 13:26 Go to last post
    • Replies: 2
    • Views: 379
    23rd September 2018, 22:57 Go to last post
  13. [Verilog] Modelsim problem of enum in simulation

    Started by sqx, 21st September 2018 05:14
    • Replies: 3
    • Views: 333
    23rd September 2018, 21:09 Go to last post
  14. FPGA Operating system

    Started by adwnis123, 8th September 2018 21:01
    2 Pages
    1 2
    • Replies: 20
    • Views: 1,138
    23rd September 2018, 04:12 Go to last post
  15. Quartus / Prime floor planning / atoms to obtain best fMax

    Started by Wiljan, 21st September 2018 09:15
    • Replies: 6
    • Views: 404
    22nd September 2018, 09:53 Go to last post
    • Replies: 5
    • Views: 413
    21st September 2018, 19:59 Go to last post
    • Replies: 2
    • Views: 275
    21st September 2018, 16:12 Go to last post
    • Replies: 0
    • Views: 135
    21st September 2018, 12:54 Go to last post