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Threads 61 to 90 of 22274

Forum: PLD, SPLD, GAL, CPLD, FPGA Design

Simple and Complex Programmable Logic Devices from Altera, Cypress, Xilinx. Field Programmable Gate Array. Device specific VHDL/Verilog/SystemC questions.

  1. Programmer and Logic Analyzer question

    Started by kkeeley, 2nd May 2018 01:00
    • Replies: 11
    • Views: 623
    3rd May 2018, 15:55 Go to last post
  2. Dose XSG can replace programming in VHDL

    Started by Serwan Bamerni, 1st May 2018 00:22
    • Replies: 4
    • Views: 421
    1st May 2018, 12:53 Go to last post
    • Replies: 8
    • Views: 896
    30th April 2018, 13:28 Go to last post
  3. [SOLVED] How to feed a grayscale image data to VGA output of an FPGA

    Started by rafimiet, 29th April 2018 12:06
    • Replies: 7
    • Views: 481
    30th April 2018, 12:01 Go to last post
  4. HSYNC and VSYNC in HDMI out port of Zedboard

    Started by rafimiet, 30th April 2018 11:58
    • Replies: 0
    • Views: 188
    30th April 2018, 11:58 Go to last post
  5. VHDL. Failed Timing. Division

    Started by Giepup, 29th April 2018 17:58
    • Replies: 3
    • Views: 299
    29th April 2018, 22:50 Go to last post
  6. Define 2 dimensional localparm in Verilog

    Started by pigtwo, 29th April 2018 03:32
    • Replies: 2
    • Views: 252
    29th April 2018, 21:19 Go to last post
  7. [SOLVED] FPGA Book for real time simulation of DC-DC converters

    Started by shomikc, 25th April 2018 11:01
    • Replies: 14
    • Views: 1,101
    29th April 2018, 10:21 Go to last post
  8. setting attributes to VHDL entity ports

    Started by shaiko, 27th April 2018 15:26
    • Replies: 3
    • Views: 318
    29th April 2018, 09:52 Go to last post
  9. synplify identify instrumentor......

    Started by velu.plg, 21st April 2018 09:57
    • Replies: 2
    • Views: 381
    28th April 2018, 13:05 Go to last post
  10. implement DFF by loop

    Started by wittman, 27th April 2018 03:22
    • Replies: 3
    • Views: 312
    27th April 2018, 16:18 Go to last post
  11. base number multiplication

    Started by sugubai, 26th April 2018 12:06
    • Replies: 1
    • Views: 187
    26th April 2018, 12:34 Go to last post
  12. Nonconstant index in Verilog

    Started by wittman, 25th April 2018 04:24
    • Replies: 3
    • Views: 370
    26th April 2018, 11:51 Go to last post
  13. [SOLVED] Glitch Filter VHDL // Lattice document

    Started by player80, 20th April 2018 14:43
    • Replies: 8
    • Views: 659
    25th April 2018, 15:20 Go to last post
  14. Usage ip core RAM Altera

    Started by agaripcan6223, 25th April 2018 13:11
    • Replies: 2
    • Views: 257
    25th April 2018, 14:08 Go to last post
  15. VHDL state machine execution

    Started by hareeshP, 21st April 2018 12:15
    • Replies: 5
    • Views: 582
    25th April 2018, 06:58 Go to last post
  16. Artix 7 xc7a35t FPGA board

    Started by ananthan95, 24th April 2018 13:02
    • Replies: 3
    • Views: 303
    24th April 2018, 13:42 Go to last post
  17. simulation problem vhdl

    Started by 7mod998, 23rd April 2018 20:35
    • Replies: 2
    • Views: 312
    24th April 2018, 10:30 Go to last post
  18. testbench without a DUT

    Started by paulr127, 19th April 2018 22:20
    • Replies: 13
    • Views: 837
    23rd April 2018, 14:36 Go to last post
  19. I have issues using a delay in VHDL

    Started by ggiacomo, 22nd April 2018 12:23
    • Replies: 3
    • Views: 359
    23rd April 2018, 09:37 Go to last post
  20. NI MyRIO with VHDL codes

    Started by pattern, 23rd April 2018 09:20
    • Replies: 0
    • Views: 194
    23rd April 2018, 09:20 Go to last post
  21. Help with this FPGA xilinx spartan xc3s50

    Started by FGDGDFGG, 18th April 2018 10:46
    • Replies: 5
    • Views: 598
    20th April 2018, 15:41 Go to last post
    • Replies: 5
    • Views: 480
    20th April 2018, 09:39 Go to last post
  22. [SOLVED] How do I read a test bench input from a txt file?

    Started by ggiacomo, 17th April 2018 09:55
    • Replies: 6
    • Views: 489
    19th April 2018, 18:39 Go to last post
  23. best method for control memory in fpga

    Started by jalal.baba, 17th April 2018 19:51
    • Replies: 5
    • Views: 513
    19th April 2018, 08:55 Go to last post
  24. altera fpga update from remote

    Started by franticEB, 18th April 2018 17:45
    • Replies: 1
    • Views: 293
    18th April 2018, 22:28 Go to last post
    • Replies: 0
    • Views: 225
    18th April 2018, 14:19 Go to last post
    • Replies: 7
    • Views: 777
    15th April 2018, 07:42 Go to last post