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Parasitic viewer - accelerating analysis and simulation of post-layout netlists

Decreasing sizes of semiconductor process geometries and greater number of metal layers, interconnections and components result in a large number of parasitic devices during netlist extraction. This can be problematic for simulation and verification engineers.

Fortunately, SPEF (standard parasitic exchange format) and DSPF (Detailed Standard Parasitic Format) interfaces can now be used through certain visualization tools to easily analyze and explore parasitic structures and to comprehend and optimize timing, signal integrity or IR-drop within their designs. SPEF file format is an IEEE standard to define parasitic networks, with precise information about interconnections and the related parasitic components.

See this video to learn how a certain SPEF interface can give design engineers specific details about the post-layout interconnections on their chips, for easier visualization and navigation of parasitic netlists and to pinpoint post-layout problems. Pruning and creating post-layout SPICE netlists of critical circuit fragments is also possible. These netlist fragments can then be used for fast circuit simulation to accelerate post layout simulation.

Parasitic cone.PNG

Comments

Visualizing a few (~ less than 10) R and C elements is pretty straightforward.
But what one can do when there are thousands or millions of those?
 
I agree this can be a daunting task and with this tool you will still see these thousand or millions of these on the net. However, you now have the ability to reduce the complexity by filtering, lumping or removing these parasitic elements to help you get a better understanding of the circuit. You can also traverse the netlist and list the heavy loaded nets from highest to lowest, or lowest to highest enabling you to focus on the nets with the largest or lowest delays. Also as mentioned in the video these single or multiple nets can be exported as separate files and simulated in simulators reducing overall simulation time. You can get more info here and you can even get a free eval if you like to check out different functions.

Sujit Roy (Field application engineer)
 
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talius
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