Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Generating Automatic Schematics from Verilog/VHDL/System Verilog

These days, digital, DFT and mixed-signal engineers have to decipher larger and more complicated System-on-Chip (SoC) functionality, with multiple RTL components and Intellectual Property (IP) blocks obtained from a variety of sources. This can consume hours of engineering time.

Comprehending another engineer's RTL code is not easy, and the right method/tool can make all the difference.

How you can visualize and explore an unknown design and easily convert your Verilog/VHDL/System Verilog netlist to schematics?

See this 4 minute video which shows signal tracing paths in incremental graphical views

You can also check out the free full simple RTL/digital netlist-to-schematics how-to series

RTL cone extraction.PNG


There are no comments to display.

Part and Inventory Search

Blog entry information

Read time
1 min read
Last update

More entries in recent entries

Share this entry