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Recent content by sixdegrees

  1. S

    LCD driver in FPGA(LTV350QV-F04 of samsung)

    ltv350qv @ Iouri What do u mean by the link above? Do these logicBricks downloadable or you want us to look at the datasheets? Or are you just one of those many engineers on this forum promoting their company's products? sixdegrees
  2. S

    Looking for a controller (VHDL) for a Monochrome 16 digits 2 lines LCD SP10Q003-T

    Re: LCD driver in FPGA can u suggest anything in Verilog and for Xilinx based devices?
  3. S

    Test vector optimization--Need Help

    You have said that you want to test any IP core but you have to first specify what fault models are u looking at, there are various types of fault models available and hundreds of test generation algorithms for the particular fault model, Also if you are venturing into SOC or Mixed Signal...
  4. S

    Whats wrong with this code?

    Can anyone tell me what is wrong with the code below? module lcd_posedge(lcd_clk_in,clk,rst,lcd_latch); input lcd_clk_in; //38 hz input clk; //main clk input rst; output lcd_latch; wire lcd_clk_in; wire clk; wire rst; wire lcd_latch; wire lcd_posedge_latch_S; wire [1:0] edge0; reg...
  5. S

    Data transfer to FPGA from computer through serial port.

    fpga 到 cpu 的数据传输 Well if u had gone through the code which i had mentioned u will see that u dont have to write anything in C, its all Verilog and yes u can transfer bits as well. But just for curiosity what type of chip are u designing/testing, I am in testing too but do mostly...
  6. S

    Data transfer to FPGA from computer through serial port.

    pc to fpga data transfer vhdl code U may also look at this link its very good indeed... **broken link removed** sixdegrees
  7. S

    Problem with timing SRAM connected to FPGA

    Re: SRAM timing Hi I built an SRAM controller few days back for the 6264 SRAM but I think the frequency was less. Regarding the slack you mention,I dont exactly understand what you mean, can u send the code so that I can try to see the problem. Also if u use ISE there is an SRAM controller for...
  8. S

    Multi cycle instructions in a RISC CPU!!

    multicycle risc processor Well as u correctly guessed it I am designing a Analog Devices ADSP 21020 processor IP core. I have a 40 bit data bus which I have to connect to an external memory like SRAM,the SRAM I am using because the controller is easier to manage. :| I have to either use 5 SRAMs...
  9. S

    Multi cycle instructions in a RISC CPU!!

    multicycling instructions Hello, I am designing a multicycle RISC CPU which has lots of instructions and various functional units. Now these instructions take variable number of clock cycles and I am required to build the controller FSM for these. I have completed all the ALU functions like...
  10. S

    What is the Distributed RAM ?

    parameterized distributed ram Yes you are right, I synthesised it in 7.1 also and it mapped to Block RAM and then I changed the synthesis style to Distributed and lo, it mapped to Distributed RAM. Maybe Xilinx people should notice this,and one more thing can you specify this constraint for...
  11. S

    What is the Distributed RAM ?

    distributed rom Well I use 7.1i so in there go to Edit->Language Constructs->VHDL/Verilog->Synthesis Constructs->Coding Examples. I am sure there will be a similar thing in 8.1 Here you will get lots of examples on how to use the various inbuilt resources like Block/Distributed Ram, Embedded...
  12. S

    Cant understand VHDL code,somebody plz convert to Verilog

    Re: Cant understand VHDL code,somebody plz convert to Verilo Thanx a lot nand_gates....I really need to learn VHDL also I think
  13. S

    Cant understand VHDL code,somebody plz convert to Verilog

    Hi! I have a code which is a controller for LCD display provided by my FPGA vendor but its written in VHDL. I have a VHDL to Verilog converter and tried using it,it converted the other two files succesfully but cant convert the top level controller. I was wondering those people who are...
  14. S

    What is the Distributed RAM ?

    infer distributed ram A little something I would like to add here is that with Xilinx you cant actually infer Distributed RAM automatically hoping the Synthesis tool will do everything for you, infact your code should be in a particular format for inferring them. For eg to instantiate a single...
  15. S

    xilinx ftp site not accessible

    eisp_pc hey i have downloaded the zip file but cant attach it, the server is giving some problems while attaching..will try later.
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